TRD Pretrigger System

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TRD Pre-trigger System
K. Oyama, M. Stockmeier, A. Rausch, and P. von
Walter for the T0, V0, and TRD Collaborations Feb
. 5, 2005 TRD Status Meeting _at_ GSI
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What is the Pre-Trigger ?

• TRD pre-trigger wakeup signal for TRD MCM's
  (not what TRD sends)
• It is generated from T0 and V0 detector signals
  using special box (shoebox).
• T0 Timing detector and M.B. trigger.
• V0 Vertex detection and M.B. trigger.
• Since timing is crucial, the shoebox is placed
  inside L3 magnet (discussed later).
• The pre-trigger shoebox should have the
  functionalities
• generate pre-trigger coincidence signal of T0
  V0 detectors.
• get TTC optical signal from outside and insert
  pre-trigger into TTC data stream.
• provide TTC optical signals to 18 TRD
  super-modules.
• in time.

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Implementation Basic

• To use TTCvi in magnet is avoided because we
  would need VME bus and VME bus master, and TTCvi
  delay inside is large.

TTC
L1, L2,
outside magnet
inside magnet
bi-phase-mark decode
pre-trigger system
bi-phase-mark encode
TRD
T0/V0
Simple Coincidence
L1, L2, pre-trigger
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Timing Constraint
CTP must receive trigger from TRD in 6 us.
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More Precise Estimation of Trigger Latency in T0
case
Until Shoebox-R INT to T0-L
3.5 m 12 ns Delay inside PMT
15 ns T0-L to Shoebox-L
1 m 5 ns Signal
processing in Sohebox-L 25
ns Shoebox-L to inner bar entrance
2.5 m 13 ns In the inner bar (in parallel to Z)
7 m 35 ns Inner bar output to
Shoebox-R 0.5 m 3 ns Subtotal
(INT to Shoebox-R) 108
ns from Wladeks calculation, it was 330 ns
if we put Shoebox outside Shoebox-RTRD Coinciden
ce in Shoebox-R 10
ns Delay in TTCvi
71 ns (69 is RD12, 71 is meas.) Optical
fan-out (TTCoc) 15
ns Delay in fiber to farthest TRD
20 m 100 ns Delay in TTCrx
50 ns Delivery of trigger to all
MCM inside chamber 25 ns Subtotal (INT to
MCM) 374 ns Inside
MCM Pre-trigger decoding and starting DAQ (to
wakeup) 150 ns (compensate ADC pipeline
del.) Total
526 ns () Blue is really estimation
and must be measured.
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Built-in Data Latency and Timing Compensation
From previous page Total trigger latency
526 ns This is the time from interaction
to the TRAP pre-processor starts to process the
data. This must be compensated somehow. Data can
be delayed by Particle traveling from IP to TRD
window 3 m 15 ns ADC pipeline
150 ns instead of 550
ns Programmable delay
100 to 600 ns in 100 ns step Cross talk
filter delay (if necessary) 200
ns Total delay of data
450 to 950 ns in 100 ns step This is the
time from the interaction to the first ADC data
from the interaction appear to the event buffer
input. In case of 950 ns (maximum), 950-526
400 ns 4 pre-samples can be taken. This is
almost satisfying our requirement (must be
checked). But 526 ns can not be more. This does
not mean we are not timing crucial detector. If
we take 950 ns, digitization ends in 950 ns 2
us 3 us after the interaction. This is
exceeding TDR requirement (2.55 us) and pushes
everything later. For example, 6 us allowed
latency of L1 from TRD could not be satisfied.
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Positions of Soeboxes
Space availability was confirmed for local
shoeboxes, and being checked for DCS Master boxes.
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Arrangement
As one of examples, we prepare 3 shoeboxes in A
side and 4 shoeboxes in C side. Each shoebox has
VME like geometry but smaller width (3 to 5
slots). There are two versions of shoeboxes
(Local pre-trigger and Master with DCS).
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T0/V0 Pre-amplifier Module
x10 output to
x1 feed-through output
Design is final. 55mm x 55mm. Three SMA
connectors. 0.5 W/ch.
power
differential output to TRD pre-trigger system
input from the PMT
30 ps resolution was achieved in the test beam
experiment. High ground and power stability are
required. Power is given from different source
with out pre-trigger system. Using inductance but
still works in the B0.5 T.
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Local Pre-trigger Box with T0 and V0
Pre-Amplifiers
top view
side view
to T0 and V0 rack
pre-amp power
VME size
T0/V0 Preamp
differential signal
disc
termination
threshold
FPGA
DAC
from detector
optional for redundancy
digital power
CLK
trig
JTAG
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Local Pre-trigger Box with T0 and V0
Pre-Amplifiers
Control
500 ps delay PECL discriminator
It can directly drive FPGA CMOS
CLK, Trig
JTAG
FPGA
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Main Control Board
Shoebox with DCS/Opt.F.O.
d210 mm
DCS -delay -control -threshold
TTC input (opt.)
TTC F.O. 2
w110 mm
Pre-Trigger to CTP (opt. or LVD)
TTC F.O. 1
DCS
h270 mm
Ethernet (cat5).
TTC ECL out to F.O. module (ECL)
JTAG to local boxes (LVD)
CLK/Control to local boxes (LVD)
Triggers from local boxes (LVD)
TTC F.O. can be TTCex or TTCex. DCS module is a
VME size board KIP DCS on it. DCS module has
also coincidence of pre-trigger of side A and C.
pre-trig to side C DCS (LVD)
ptre-trig from side A DCS (LVD)
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Fault Tolerance
System I
- System may have malfunctioning due to
radiation, B field, and normal problems. - We
loose entire TRD data if we loose the pre-trigger
system. - We can consider to have duplication of
all digital part (without analog
part). Duplicated part (System II) is identical
to System I and run independently. Two optical
fibers should go to each TRD super-module and
merged inside, it is possible (study by Marc).
System II
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Conslusions

• Pre-amplifier design is fixed!
• Conceptual design was fixed!
• Prototype of local shoebox will be available
  soon.
• Prototype development of DCS master shoebox is
  now started.
• Action items
• Check possibility whether everything fits inside
  mechanically
• cabling space (at least 50 mm around), power
  space must be checked.
• Cooling
• Radiation tests Nothing was tested except for
  DCS (includes TTCrx and FPGA on it).
• Test of delay implementations in FPGA.
• Precise measurement of trigger latency should be
  done.
• Study of feasibility of applying DCS to our
  purpose of pins looks ok.
• CTP interface must be fixed (at least
  physically).
• Simulation study is needed to ensure T0/V0
  triggers
• and pre-trigger have almost same trigger bias.

T0/V0 trigger
pre-trigger
This can not happen!