Chapter 5 The Processor: Datapath and Control

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Chapter 5The Processor Datapath and Control
Computer Organization

• Kevin Schaffer
• Department of Computer Science
• Hiram College

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MIPS Subset

• Memory access instructions
• lw, sw
• Arithmetic and logic instructions
• add, sub, and, or, slt
• Branch instructions
• beq, j

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Instruction Formats
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Fetch-Decode-Execute

• In order to execute an instruction we must
• Fetch the instruction from memory
• Determine what the instruction is (decode)
• Execute it
• Fetch and decode are the same for all
  instructions
• Execute depends on the type of instruction

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Executing Arithmetic/Logic

• Arithmetic/logic (add, sub, and, or, slt)
• Fetch operands from registers
• Perform operation
• Write result back to register

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Executing Load and Store

• Load
• Fetch operand (base address) from register
• Compute effective address
• Read data from memory
• Write result back to register
• Store
• Fetch operands from registers
• Compute effective address
• Write data to memory

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Executing Branch and Jump

• Conditional branch (beq)
• Fetch operands from registers
• Compare operands
• If equal add displacement to PC
• Jump (j)
• Write new value to PC

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Instruction Fetch

• Components
• Instruction Memory
• Program Counter (PC)
• Adder
• Operation
• Fetch the instruction whose address is in the PC
• Increment the PC by 4

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Instruction Fetch
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Instruction Fetch
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ALU Instructions

• Components
• Register File
• ALU
• Operation
• Use instruction fields to select registers
• Read source registers and send them to ALU
• Send ALU result to destination register

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ALU Instructions
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Load and Store

• Components
• Register File
• ALU
• Data Memory
• Sign-Extension Unit
• Operation
• ALU adds base register and sign-extended
  immediate
• Read value from memory into destination register
  (lw) or write value from source register into
  memory (sw)

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Load and Store
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Branches

• Components
• Register File
• ALU
• Program Counter (PC)
• Adder
• Sign-Extension Unit
• Operation
• Send source register values to ALU for comparison
• Adder computes branch target address
• Control logic decides whether branch is taken or
  not

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Branches
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Execution Datapath
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Putting It All Together
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ALU Control

• In order to simplify design of the main control
  unit we give the ALU its own control logic
• The ALU control block takes a 2-bit control
  signal (ALUOp) and the instruction's funct field
• Generates a 4-bit operation code for ALU

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ALU Control
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ALU Control
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ALU Control
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Control Unit

• Control unit takes an instruction as input and
  produces control signals as output
• Types of control signals
• Multiplexor selector signals
• Write enables for state elements
• Control signals for other blocks (ALU, etc.)
• In a single-cycle datapath the control unit is
  simple, just look up instruction in a table

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Control Signals

• RegDst Selects either rd or rt as the
  destination register
• RegWrite The value on the write data port will
  be written into the register specified by the
  write register input when asserted
• ALUOp Selects ALU operation
• ALUSrc Selects the second ALU input to be either
  the second register output or the sign-extended
  immediate value

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Control Signals

• PCSrc Selects new PC as either PC 4 or the
  output of the branch target adder
• Logical AND of Branch control signal and ALU Zero
  output
• MemRead/MemWrite Causes data memory to perform a
  read/write operation when asserted
• MemtoReg Selects either the ALU output or the
  data memory output as the data input into the
  register file

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Control Signals
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Control Logic
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Datapath with Control Unit
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Executing an ALU Instruction
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Executing a Load
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Executing a Branch
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Jump

• The unconditional branch instruction (j) computes
  its branch target differently from the
  conditional branch instruction (beq)
• Branch target address is
• Top 4 bits of PC 4
• 26-bit immediate value, shifted left 2 places
• Add a new control signal Jump

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Jump
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More Instructions

• What changes would be needed to implement these
  instructions?
• addi
• nor
• jr

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Performance

• Single-cycle datapath executes each instruction
  in one cycle (CPI is 1)
• Time to execute an instruction is sum of delays
  of functional units used
• Clock cycle time must be long enough to
  accommodate the slowest instruction

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Functional Unit Use
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Using Multiple Cycles

• A multicycle datapath splits instruction
  execution into multiple steps, where each step
  take one cycle
• Can skip steps that are not needed, so
  instructions can take different number of cycles
  to execute
• Slow instructions don't slow down the entire
  processor
• Can share hardware between steps
• However, control unit becomes more complicated

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Multicycle Datapath
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Multicycle Differences

• A functional unit can be used more than once in
  the execution of an instruction, so long as those
  uses occur in different steps
• Instruction memory and data memory are combined
  into a single unit
• ALU takes over for the two separate adders
• Additional registers are needed to save
  information between steps

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Multicycle Datapath
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Multicycle Datapath
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Multicycle Datapath
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New Registers

• Instruction register (IR) hold the instruction
  during its execution
• Memory data register (MDR) hold the data read
  from memory for one cycle
• A hold source register for one cycle
• B hold source register for one cycle
• ALUOut hold ALU output for one cycle

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New Control Signals

• ALUSrcA selects first ALU operand to be either
  the PC or the A register
• ALUSrcB selects second ALU operand from B
  register, constant 4, sign-extended immediate,
  sign-extended and shifted immediate
• MemtoReg selects register file write data as
  coming from either ALUOut or MDR
• IorD selects the memory address as coming from
  either PC or ALUOut

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New Control Signals

• IRWrite If asserted the memory output is written
  to IR
• PCSource Selects the new value for the PC from
  ALU, ALUOut, jump target address
• PCWrite If asserted the PC is written
• PCWriteCond If asserted and the zero output from
  the ALU is 1 then the PC is written

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Instruction Execution Steps

• Instruction fetch
• Instruction decode and register fetch
• Execution, memory address computation, or branch
  completion
• Memory access or R-type completion
• Memory read completion

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Instruction Fetch

• Fetch instruction from memory
• IR ? MemoryPC
• Increment the PC
• PC ? PC 4

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Instruction Decode

• Fetch operands from register file
• A ? RegIR2521
• B ? RegIR2016
• Compute branch target address
• ALUOut ? PC (SignExt(IR150) ltlt 2)

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Execute

• Load/store Compute memory address
• ALUOut ? A SignExt(IR150)
• R-type Perform operation specified by
  instruction
• ALUOut ? A op B
• Branch Compare registers and set PC if equal
• if (A B) PC ? ALUOut
• Jump Set PC to jump target address
• PC ? PC3128, (IR250 ltlt 2)

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Memory Access

• Load Read memory word into MDR
• MDR ? MemoryALUOut
• Store Write B into memory
• MemoryALUOut ? B
• R-type Write result to destination register
• RegIR1511 ? ALUOut

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Memory Read Completion

• Load Write result to destination register
• RegIR2016 ? MDR

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State Machine

• A state machine is a sequential logic device
  with
• Set of states
• Next-state function which determines the next
  state from the current state and the inputs
• Output function which determines the outputs from
  the current state and possibly the inputs
• In a Moore machine the output depends only on the
  state in a Mealy machine the output depends on
  the state and the inputs

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Control Unit

• The control unit for our multicycle datapath will
  be a state machine
• The only input is the op field of the
  instruction the outputs are the control signals
• Each step may have multiple states if control
  signals depend on the instruction

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Control Unit
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State Machine
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Fetch and Decode States
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Load and Store States
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R-Type States
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Branch State
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Jump State
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Complete State Machine
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Exceptions

• An exception is an event that causes an
  unscheduled transfer of control
• Also known as interrupts and traps
• Typically an interrupt is caused externally while
  an exception or trap is caused internally
• Arithmetic overflow is an example of an
  exception an I/O device request is an example of
  an interrupt

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Handling Exceptions

• When hardware detects an exception it transfers
  control to a software routine called an exception
  handler which is typically a part of an operating
  system
• The hardware saves the value of the PC in the
  exception PC (EPC) register so it can return
  there after the exception is handled

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Determining the Cause

• The hardware must tell the exception handler what
  the cause of the exception was
• One way to do this is store a value into a
  special Cause register (MIPS)
• Another way is to use vectored interrupts where
  control is transferred to a different address
  depending on the cause

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Exceptions to Implement

• Undefined instruction occurs when the op field of
  an instruction indicates an undefined or
  unimplemented instruction
• Arithmetic overflow occurs when the ALU detects
  an overflow during an R-type instruction

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Adding Exception Support

• EPC register saves the old PC it is written when
  EPCWrite is asserted
• Cause register records the cause of the
  exception it is written when CauseWrite is
  asserted
• IntCause indicates the cause of the exception
• Control is always transferred to 0x80000180

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Adding Exception Support
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Adding Exception Support
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Microprogramming

• An alternative to state machines for control is
  microprogramming
• Each instruction is implemented as a sequence of
  microinstructions (a microprogram)
• The opcode bits specify the starting address of
  the microprogram within the microcode ROM.
• A microinstruction contains values for all of the
  control signals plus some sequencing control bits

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Microinstruction Fields
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Microcode Example
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Microprogrammed Control
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Multicycle Performance

• The multicycle datapath has a much shorter clock
  cycle time than the single-cycle datapath
• Clock cycle time based on longest step instead of
  longest instruction
• However, it also has a larger CPI
• Is the multicycle datapath really faster?
• Can we still do better?