Datapath and Control Chapter 5

1
Datapath and ControlChapter 5

• Vishwani D. Agrawal
• James J. Danaher Professor
• Department of Electrical and Computer Engineering
• Auburn University
• http//www.eng.auburn.edu/vagrawal
• vagrawal_at_eng.auburn.edu

2
Von Neumann Kitchen
Start
ALU
Control
Registers
My choice
PC
Processor
Program
Data
Memory
Output
3
Where Does It All Begin?

• In a register called program counter (PC).
• PC contains the memory address of the next
  instruction to be executed.
• In the beginning, PC contains the address of the
  memory location where the program begins.

4
Where is the Program?
Memory
Processor
Program counter (register)
Machine code of program
Start address
5
How Does It Run?
Start
Fetch instruction word from memory address in PC
and increment PC ? PC 4
Decode and execute instruction
Program complete?
Yes
No
STOP
6
Datapath and Control

• Datapath Memory, registers, adders, ALU, and
  communication buses. Each step (fetch, decode,
  execute) requires a communication (data transfer)
  path between memory, registers and ALU.
• Control Datapath for each step is set up by
  control signals that control communication bus
  and select ALU function. Control signals are
  generated by a control unit consisting of one or
  more finite-state machines.

7
Datapath for Instruction Fetch
4
Instruction Memory
PC
Instruction word to control unit and registers
Address
8
Register File
5
32 Registers (reg. file)
reg 1
Read register numbers
32
reg 1 data
5
reg 2
Write register number
5
32
reg 2 data
Write data
32
9
Multi-Operation ALU
Operation select from control
Operation select ALU function 000 AND
001 OR 010 Add 110 Subtract 111 Set on
less than
3
zero
ALU
result
overflow
zero 1, when all bits of result are 0
10
Test 1 Result
Average score20.6 (Max24)
11
R-Type Instructions

• Also known as arithmetic-logical instructions
• add, sub, slt
• Example add t0, s1, s2
• Machine instruction word
• 000000 10001 10010 01000 00000 100000
• opcode s1 s2 t0 function
• Read two registers
• Write one register
• Opcode and function code go to control unit that
  generates RegWrite and ALU operation code.

12
Datapath for R-Type Instruction
000000 10001 10010 01000 00000 100000 opcode
s1 s2 t0 function
Operation select from control
32 Registers (reg. file)
5

10001
s1
Read register numbers
3
32
zero
5
s2
10010
ALU
result
32
overflow
Write reg. number

5
t0
01000
Write data
32
13
Load and Store Instructions

• I-type instructions
• lw t0, 1200 (t1)
• 100011 01001 01000 0000 0100 1000 0000
• opcode t1 t0 1200
• sw t0, 1200 (t1)
• 101011 01001 01000 0000 0100 1000 0000
• opcode t1 t0 1200

14
Datapath for lw Instruction
100011 01001 01000 0000 0100 1000 0000 opcode
t1 t0 1200
MemWrite
Operation select from control
32 Registers (reg. file)

5
01001
t1
Read register numbers
3
Read data
32
zero
5
result
ALU
Addr.
Data memory
overflow

Write reg. number
5
t0
01000
Write data
Write data
32
32
RegWrite from control
Sign extend
MemRead
0000 0100 1011 0000
16
mem. data to t0
15
Datapath for sw Instruction
101011 01001 01000 0000 0100 1000 0000 opcode
t1 t0 1200
MemWrite
Operation select from control
32 Registers (reg. file)

5
01001
t1
Read register numbers
3
Read data
32
zero
5
t0
result
01000
ALU
Addr.
Data memory
overflow

Write reg. number
5
32
Write data
Write data
t0 data to mem.
32
32
Sign extend
RegWrite from control
MemRead
0000 0100 1011 0000
16
16
Branch Instruction (I-Type)

• beq s1, s2, 25 if s1s2, advance
  PC through 25 instructions
• 16-bits
• 000100 10001 10010 0000 0000 0001 1001
• opcode s1 s2 25

Note Can branch within 215 words from the
current instruction address in PC.
17
Datapath for beq Instruction
16-bits 000100 10001 10010 0000 0000 0001
1001 opcode s1 s2 25
Operation select from control
32 Registers (reg. file)
5
10001
s1
Read register numbers

32
5
s2
To branch control logic
10010
zero
result
5
32
Write reg. number
overflow
Write data
PC4
Branch target
32
RegWrite from control
From instruction fetch datapath
32
Sign extend
Shift left 2
16
0000 0000 0001 1001
32
32

32
18
J-Type Instruction

• j 2500 jump to instruction 2,500
• 26-bits
• 000010 0000 0000 0000 0010 0111 0001 00
• opcode 2,500

32-bit jump address
0000 0000 0000 0000 0010 0111 0001 0000
bits 28-31 from PC4
19
Datapath for Jump Instruction
Branch
Jump
Branch addr.
32
4
1 mux 0
32
32
PC4
4
Shift left 2
28
Instruction Memory
32
PC
opcode (bits 26-31) to control
26
32
6
Address
32
Instruction word to control and registers
20
Jump
0-25
Shift left 2
0 mux 1
4
Add
1 mux 0
ALU
Branch
opcode
MemtoReg
CONTROL
RegDst
26-31
21-25
MemWrite MemRead
zero
ALU
Instr. mem.
PC
Reg. File
Data mem.
1 mux 0
16-20
0 mux 1
1 mux 0
11-15
Combined Datapaths
ALU Cont.
Sign ext.
Shift left 2
0-15
0-5
21
Control
RegDst Jump Branch MemRead MemtoReg ALUOp Me
mWrite ALUSrc RegWrite
Instruction bits 26-31 opcode
Control Logic
2
Instruction bits 0-5 funct.
ALUControl
to ALU
22
Control Logic Truth Table
Instr type Inputs instr. opcode bits Inputs instr. opcode bits Inputs instr. opcode bits Inputs instr. opcode bits Inputs instr. opcode bits Inputs instr. opcode bits Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals Outputs control signals
Instr type 31 30 29 28 27 26 RegDst Jump ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALOOp1 ALUOp2
R 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0
lw 1 0 0 0 1 1 0 0 1 1 1 1 0 0 0 0
sw 1 0 1 0 1 1 X 0 1 X 0 0 1 0 0 0
beq 0 0 0 1 0 0 X 0 0 X 0 0 0 1 0 1
j 0 0 0 0 1 0 X 1 X X X X X X X X
23
How Long Does It Take?

• Assume control logic is fast and does not affect
  the critical timing. Major time components are
  ALU, memory read/write, and register read/write.
• Arithmetic-type (R-type)
• Fetch (memory read) 2ns
• Register read 1ns
• ALU operation 2ns
• Register write 1ns
• Total 6ns

24
Time for lw and sw (I-Types)

• ALU (R-type) 6ns
• Load word (I-type)
• Fetch (memory read) 2ns
• Register read 1ns
• ALU operation 2ns
• Get data (mem. Read) 2ns
• Register write 1ns
• Total 8ns
• Store word (no register write) 7ns

25
Time for beq (I-Type)

• ALU (R-type) 6ns
• Load word (I-type) 8ns
• Store word (I-type) 7ns
• Branch on equal (I-type)
• Fetch (memory read) 2ns
• Register read 1ns
• ALU operation 2ns
• Total 5ns

26
Time for Jump (J-Type)

• ALU (R-type) 6ns
• Load word (I-type) 8ns
• Store word (I-type) 7ns
• Branch on equal (I-type) 5ns
• Jump (J-type)
• Fetch (memory read) 2ns
• Total 2ns

27
How Fast Can the Clock Be?

• If every instruction is executed in one clock
  cycle, then
• Clock period must be at least 8ns to perform the
  longest instruction.
• This is a single cycle machine.
• It is slower because many instructions take less
  than 8ns but are still allowed that much time.
• Method of speeding up Use multicycle datapath.

28
A Single Cycle Example
Delay of 1-bit full adder 1ns Clock period
32ns
a31 . . . a2 a1 a0
c32
1-b full adder
s31 . . . s2 s1 s0
1-b full adder
b31 . . . b2 b1 b0
1-b full adder
1-b full adder
Time of adding words 32ns Time of adding
bytes 32ns
0
29
A Multicycle Implementation
a31 . . . a2 a1 a0
Delay of 1-bit full adder 1ns Clock period
1ns Time of adding words 32ns Time of adding
bytes 8ns
Shift
1-b full adder
b31 . . . b2 b1 b0
s31 . . . s2 s1 s0
c32
FF
Shift
Shift
Initialize to 0
30
Multicycle Datapath
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUOut Reg.
Data
4
Mem. Data (MDR)
B Reg.
One-cycle paths
31
Multicycle Datapath Requirements

• Only one ALU, since it can be reused.
• Single memory for instructions and data.
• Five registers added
• Instruction register (IR)
• Memory data register (MDR)
• Three ALU registers, A and B for inputs and
  ALUOut for output

32
Multicycle Datapath
PCSource
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcB
ALUSrcA
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst
control
MUX
4
IRWrite
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg
0-15
MemWrite
ALU control
ALUOp
0-5
33
I got the idea for the _______ while attending
a talk at a computer conference. The speaker was
so boring that I started daydreaming and and hit
upon the idea. Doug Engelbart inventor of
computer mouse
34
1-bit Control Signals
Signal name Value 0 Value 1
RegDst Write reg. bit 16-20 Write reg. bit 11-15
RegWrite No action Write reg. ? Write data
ALUSrcA First ALU Operand ? PC First ALU Operand?Reg. A
MemRead No action Mem.Data Output?MAddr.
MemWrite No action MAddr.?Mem. Data Input
MemtoReg Reg.File Write In?ALUOut Reg.File Write In?MDR
IorD Mem. Addr. ? PC Mem. Addr. ? ALUOut
IRWrite No action IR ? Mem.Data Output
PCWrite No action PC is written
PCWriteCond No action PC is written if zero(ALU)1
zero(ALU)
PCWriteCond
PCWrite etc.
PCWrite
35
2-bit Control Signals
Signal name Value Action
ALUOp 00 ALU performs add
ALUOp 01 ALU performs subtract
ALUOp 10 Funct. field (0-5 bits of IR ) determines ALU operation
ALUSrcB 00 Second input of ALU ? B reg.
ALUSrcB 01 Second input of ALU ? 4 (constant)
ALUSrcB 10 Second input of ALU ? 0-15 bits of IR sign ext. to 32b
ALUSrcB 11 Second input of ALU ? 0-15 bits of IR sign ext. and left shift 2 bits
PCSource 00 ALU output (PC 4) sent to PC
PCSource 01 ALUOut (branch target addr.) sent to PC
PCSource 10 Jump address IR0-25 shifted left 2 bits, concatenated with PC428-31, sent to PC
36
3 to 5 Cycles for an Instruction
Step R-type (4 cycles) R-type (4 cycles) Mem. Ref. (4 or 5 cycles) Mem. Ref. (4 or 5 cycles) Branch type (3 cycles) Branch type (3 cycles) J-type (3 cycles)
Instruction fetch IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4 IR ? MemoryPC PC ? PC4
Instr. decode/ Reg. fetch A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2 A ? IR21-25 B ? IR16-20 ALUOut ? PC (sign extend IR0-15) ltlt 2
Execution, addr. Comp., branch jump completion ALUOut ? A op B ALUOut ? Asign extend (IR0-15) ALUOut ? Asign extend (IR0-15) If (A B) then PC?ALUOut If (A B) then PC?ALUOut PC?PC28-31 (IR0-25ltlt2) PC?PC28-31 (IR0-25ltlt2)
Mem. Access or R-type completion IR11-15? ALUOut MDR?MALUout or MALUOut ?B MDR?MALUout or MALUOut ?B
Memory read completion IR16-20 ? MDR IR16-20 ? MDR
37
Control Finite State Machine
Start
State 0
Clock cycle 1
Instruction fetch
State 1
Clock cycle 2
Instruction decode and register fetch
FSM-M
Memory access instr.
FSM-R
FSM-B
FSM-J
Clock cycles 3-5
R-type instr.
Branch instr.
Jump instr.
38
State 0 Instruction Fetch (CC1)
PCSource00
PCWrite etc.1
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcB01
ALUOut Reg.
ALUSrcA0
IorD0
Data
Mem. Data (MDR)
B Reg.
out
RegDst
control
MUX
4
IRWrite 1
Add
in1
in2
Sign extend
Shift left 2
MemRead 1
MemtoReg
0-15
ALUOp 00
MemWrite
ALU control
0-5
39
State 0 Control FSM Outputs
Start
State 1 Instruction decode/ Register
fetch/ Branch addr.
State0 Instruction fetch
Outputs?
40
State 1 Instr. Decode/Reg. Fetch/ Branch Address
(CC2)
PCSource
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcA0
ALUSrcB11
ALUOut Reg.
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst
control
MUX
Add
4
IRWrite
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg
0-15
ALUOp 00
MemWrite
ALU control
0-5
41
State 1 Control FSM Outputs
Start
State 1 Instruction decode/ Register
fetch/ Branch addr.
State0 Instruction fetch
ALUSrcA 0 ALUSrcB 11 ALUOp 00
Opcode lw, sw
Opcode R-type
Opcode J-type
Opcode BEQ
42
State 1 (Opcodelw) ? FSM-M (CC3-5)
PCSource
CC4
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite1
21-25
28-31
16-20
CC3
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcA1
ALUSrcB10
ALUOut Reg.
IorD1
Data
Mem. Data (MDR)
B Reg.
out
CC5
control
MUX
Add
4
IRWrite
RegDst0
in1
in2
Sign extend
Shift left 2
MemRead1
MemtoReg1
0-15
ALUOp 00
MemWrite
ALU control
0-5
43
State 1 (Opcodesw)?FSM-M (CC3-4)
CC4
PCSource
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
CC3
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcA1
ALUSrcB10
ALUOut Reg.
IorD1
Data
Mem. Data (MDR)
B Reg.
out
RegDst0
control
MUX
Add
4
IRWrite
CC4
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg
0-15
ALUOp 00
MemWrite1
ALU control
0-5
44
FSM-M (Memory Access)
From state 1 Opcode lw or sw
Compute mem addrress
ALUSrcA 1 ALUSrcB 10 ALUOp 00
Opcode lw
Opcode sw
Read Memory data
Write memory
MemRead 1 IorD 1
MemWrite 1 IorD 1
Write register
To state 0 (Instr. Fetch)
RegWrite 1 MemtoReg 1 RegDst 0
45
State 1(OpcodeR-type)?FSM-R (CC3-4)
PCSource
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcA1
ALUSrcB00
CC3
ALUOut Reg.
11-15
IorD
Data
Mem. Data (MDR)
B Reg.
out
RegDst0
control
MUX
4
IRWrite
funct. code
CC4
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg0
0-15
ALUOp 10
MemWrite
ALU control
0-5
46
FSM-R (R-type Instruction)
From state 1 Opcode R-type
ALU operation
ALUSrcA 1 ALUSrcB 00 ALUOp 10


Write register
To state 0 (Instr. Fetch)
RegWrite 1 MemtoReg 0 RegDst 1
47
State 1 (Opcodebeq) ? FSM-B (CC3)
If(zero)
PCSource 01
PCWrite etc.1
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
ALU
Register file
ALUSrcA1
ALUSrcB00
CC3
ALUOut Reg.
11-15
IorD
Data
Mem. Data (MDR)
zero
B Reg.
out
RegDst
control
MUX
4
IRWrite
subtract
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg
0-15
ALUOp 01
MemWrite
ALU control
0-5
48
Write PC on zero
zero1
PCWriteCond1
PCWrite etc.1
PCWrite
49
FSM-B (Branch)
From state 1 Opcode beq
Write PC on branch condition
Branch condition If A B0 zero 1
ALUSrcA 1 ALUSrcB 00 ALUOp
01 PCWriteCond1 PCSource01


To state 0 (Instr. Fetch)
50
State 1 (Opcodej) ? FSM-J (CC3)
CC3
PCSource 10
PCWrite etc.
Shift left 2
26-31 to Control FSM
0-25
RegWrite
21-25
28-31
16-20
PC
Instr. reg. (IR)
A Reg.
Addr.
Memory
Register file
ALU
ALUOut Reg.
ALUSrcA
11-15
ALUSrcB
IorD
Data
Mem. Data (MDR)
zero
B Reg.
out
RegDst
control
MUX
4
IRWrite
in1
in2
Sign extend
Shift left 2
MemRead
MemtoReg
0-15
ALUOp
MemWrite
ALU control
0-5
51
Write PC
zero
PCWriteCond
PCWrite etc.1
PCWrite1
52
FSM-J (Jump)
From state 1 Opcode jump
Write jump addr. In PC
PCWrite1 PCSource10


To state 0 (Instr. Fetch)
53
Control FSM
Start
State 0
1
lw or sw
J
R
B
2
3
lw
6
8
9
sw
4
5
7
54
Control FSM (Controller)
6 inputs (opcode)
16 control outputs
Combinational logic
Next state
Present state
Reset
Clock
FF
FF
FF
FF
55
Designing the Control FSM

• Encode states need 4 bits for 10 states, e.g.,
• State 0 is 0000, state 1 is 0001, and so on.
• Write a truth table for combinational logic
• Opcode Present state Control signals Next state
• 000000 0000 1100110000100000 0001
• . . . . . . . . . . . . . . . .
• Synthesize a logic circuit from the truth table.
• Connect four flip-flops between the next state
  outputs and present state inputs.

56
Block Diagram of a Processor
MemWrite MemRead
Controller (Control FSM)
ALU control
ALUOp 2-bits
funct. 0,5
Opcode 6-bits
ALUOp 3-bits
PCSource 2-bits
ALUSrcB 2-bits
IorD
ALUSrcA
RegWrite
zero
PCWrite
RegDst
Overflow
MemtoReg
IRWrite
PCWriteCond
Datapath (PC, register file, registers, ALU)
Reset Clock
Mem. Addr. Mem. write data Mem. data out
57
Exceptions or Interrupts

• Conditions under which the processor may produce
  incorrect result or may hang.
• Illegal or undefined opcode.
• Arithmetic overflow, divide by zero, etc.
• Out of bounds memory address.
• EPC 32-bit register holds the affected
  instruction address.
• Cause 32-bit register holds an encoded exception
  type. For example,
• 0 for undefined instruction
• 1 for arithmetic overflow

58
Implementing Exceptions
PCSource 11
8000 0180(hex)
PCWrite etc.1
26-31 to Control FSM
PC
Instr. reg. (IR)
EPCWrite1
ALU
ALUSrcA0
ALUSrcB01
EPC
CauseWrite1
Overflow to Control FSM
out
0
control
MUX
4
Cause
1
Subtract
in1
in2
ALUOp 01
ALU control
59
Next Microprogramming
An alternative implementation of the controller.