Path Delay Test Compaction with Process Variation Tolerance

1
Path Delay Test Compaction with Process Variation
Tolerance

• Design Automation Conference
• June 16, 2005
• Seiji Kajihara Masayasu Fukunaga Xiaoqing Wen
  
• (Kyushu Institute of Technology, JAPAN)
• Toshiyuki Maeda Shuji Hamada Yasuo Sato
• (STARC, JAPAN)

2
Outline

• Introduction
• Path selection in path delay testing
• Test pattern compaction in ATPG
• Purpose of this work
• Proposed Method
• Basic idea of the proposed method
• Advantages of the proposed method
• Experimental Results
• Conclusions

3
Background

• Defects affecting timing behavior are becoming
  dominant for DSM circuits.
• Path Delay Fault Model the increased delay of a
  path between two FFs.
• Test patterns generated for path delay faults can
  detect many other types of delay faults.

FF
Fault-Free
FF
Faulty
Capture
4
Path Delay Testing Issue - 1

• The number of paths is too large to allow
  efficient test pattern generation if all paths
  are targetedin ATPG.
• 16-Bit Multiplier2000 gates / 1019 paths
• Only a subset of paths can be targeted Path
  Selection

5
Paths and Untestable Paths
Circuit paths untestable unt. time C880 17,284
163 0.94 1 C3540 57,353,342 37,869,721 66.0 9 C62
88 1.978E20 1.977E20 99.9 71 S13207 2,690,738
1,946,331 72.3 41 S15850 3.29E08 2.75E
08 83.6 60 S35932 394,282 270,057 68.4 493 S38417
2,783,158 861,860 30.9 224 S38584 2,161,446 1,47
0,244 63.3 450 Runtime (sec.) was measured on
HP735 Kajihara, VLSID97

• The number of remaining paths which are not
  identified as untestable is still large.

6
Path Selection Methods

• N Longest Paths in a Circuit
• Select N longest paths in the order of path
  lengths.
• The selected paths may not be distributed all
  over the circuit and may be locally concentrated
  in a part of the circuit.
• Longest Path through Each Line
• Contains at least one of the longest paths
  through each line.
• Statistical Method / Dynamic Method
• Two Path Sets

7
Path Delay Testing Issue - 2 3

• Process Variation
• Structurally longest paths may not be actual
  longest paths in a manufactured circuit due to
  process variation.
• It is difficult to know exact delay distribution
  of manufactured circuits.
• The longest paths may be different for each
  manufactured circuit.
• Statistical path selection approaches are still
  insufficient.
• Test Set Size
• The number of tests is usually large.
• The reasons are that a two-pattern test is
  required to detect one delay fault and that the
  constraints for the patterns are stronger than
  those for stuck-at faults.

8
Related Work Test Compaction

• A procedure to reduce the size of a test set
  without causing fault coverage loss.
• Dynamic Compaction
• Using unspecified values in a test cube to detect
  other faults during ATPG.
• test for the primary fault 0xx1xx0
• test for one secondary fault 01x1x00
• test for one more secondary fault 0101100
• Static Compaction
• Merging multiple tests into one after ATPG.
• test for a fault 0x10
• test for another fault x1x0
• Merged test 0110

9
Goal of Our Work
All Faults
Path Selection
Target Faults
ATPG
Initial Test Set
Static Compaction
Compacted Test Set
Increase Accidental Detection
Coverage of Targeted Faults
Compacted
Initial
of tests
10
Problem Statement

• Input
• Circuit the netlist of a full scan circuit
• Target Fault List selected by a path selection
  criterion
• Initial Test Set uncompacted
• Output
• Compacted Test Set
• Fault coverage for the target fault list remains
  unchanged.
• The number of two-pattern tests are small.
• The number of accidental detections is large.

11
Outline

• Introduction
• Path selection in path delay testing
• Test pattern compaction in ATPG
• Purpose of this work
• Proposed Method
• Basic idea of the proposed method
• Advantages of the proposed method
• Experimental Results
• Conclusions

12
Basic Idea of Our Method

• Simultaneous Testing and Target Path Crossing
• Case 1 (simultaneous / no-crossing)
• Case 2 (simultaneous / crossing)

13
Accidental Detection

• When two target paths with a common gate are
  tested simultaneously with the same test, paths
  other than the two target paths may also be
  tested.

p1
p3
p1
p2
p4
Common Gate
p2
14
Common Gate

• p1 and p2 are tested by the same two-pattern
  test.
• Simultaneous testing achieved by dynamic
  (multi-targeting) or static compaction (merging).
• Certain conditions need to be satisfied at the
  common gate in order for accidental detection to
  occur.

Common Gate
15
Conditions for Accidental Detection

• The common gate has fanout branches.
• Two paths have the same type of transition
  at the inputs of the common gate.
• The transition at the common gate is from the
  controlling value to the non-controlling value.

Transition from CV to NCV
Transition from NCV to CV
16
Example
Common Gate
All three conditions are satisfied.
17
Increasing Accidental Detection

• The more common gates (with fanout branches),
  the more accidental detections.

4 paths are tested
8 paths are tested
18
Advantages

• Smaller Number of Two-Pattern Tests
• Better Process-Variation-Tolerance Capability
• With many accidental detections related to target
  paths (longest by analysis), the chances of
  detecting a real critical path (longest by
  fabrication) in a manufactured circuit are higher.

p1
p3
p2
Targeted Paths in ATPG
Longest Path in a manufactured circuit
19
Outline

• Introduction
• Path selection in path delay testing
• Test pattern compaction in ATPG
• Purpose of this work
• Proposed Method
• Basic idea of the proposed method
• Advantages of the proposed method
• Experimental Results
• Conclusions

20
Experimental Results

• Circuits
• Full-scan version of ISCAS89 benchmark circuits
• Conditions of Delay Fault Testing
• Two-pattern test application enhanced scan
• Path sensitization non-robust
• Target Fault List
• Longest path through each line
• Test Compaction Technique Used
• Simple static compaction

21
Static Compaction Flow - Ours
All Faults
Path Selection
Target Faults
ATPG (one target fault per test / keep dont care
bits)
Initial Test Set
Static Compaction (find two compatible tests
whose target paths
have the largest number of common gates,
and merge them into one test)
Compacted Test Set with many accidental detections
22
Comparison Flow - Uncompact
All Faults
Path Selection
Target Faults
ATPG (- one target fault per test -
random X-filling for all dont care bits
- fault-simulation-based fault dropping)
Test Set
23
Statistics of Circuits and Faults
24
Tests and Fault Efficiency
Test set sizes were reduced approximately to 25
of those of the uncompact test sets while the
uncompact test sets have a little higher fault
efficiency.
25
Effects of the Proposed Method
For circuits s15850 and s38584, the compacted
tests could test more paths than the uncompact
test sets, with a smaller number of test
patterns.
26
Effects of the Proposed Method
27
Conclusions

• A Test Compaction Technique for Path Delay
  Testing
• Reducing the number of tests
• Improving the process-variation-tolerance
  capability
• Key Idea
• Simultaneous testing of target paths with as many
  common gates as possible
• Future Work
• Better static compaction algorithm
  implementation
• More experiments
• Extension to dynamic compaction