DefectDesign Learning from Electrical Test

1
Defect/Design Learning fromElectrical Test

• Dr. Bernd Koenemann
• Mentor Graphics Corporation

2
Agenda

• Part I
• Introduction
• Defects and Technology Challenges
• Part II
• Defect Learning
• Background
• Enhanced Learning with Test
• Total Analysis Vision
• Summary

3
Part I
4
Defect Types and Potential Sources
Parametric
Catastrophic
Spot Defects Design Logic Bugs
Physical (BEOL/FEOL/Track)- Chip-to-Chip-
Across Chip Model ? H/W Correlation Design Timing
Bugs
Static
From R.Puri, IBM
5
Spot Defects Particles

• Caused by dirt/impurities, and/or
  equipment/material problems
• E.g., particle contamination causes a short
• May be visible to in-line inspection tools
• Can be characterized by test structures
• Create catastrophic or parametric defects
• Area-sensitive (critical area)

From Skumanich and Ryabova, ASMC 2002
6
Feature-Based Yield
Particle Defect-driven vs. Feature-driven
Yield Failure to form features replaces particle
defects as the problem
100
Traditional defect-limitedyield
90
80
Product yield
70
60
.13?m
0.8?m
0.5?m
0.35?m
0.25?m
.18?m
90nm
From PDF Solutions
7
Sub-Wavelength Lithography
Lithography
Lithography
365nm
365nm
Wavelength
Wavelength
248nm
248nm
193nm
193nm
180nm
180nm
130nm
130nm
90nm
90nm
65nm
65nm
FeatureSize
45nm
45nm
32nm
32nm
13nm
13nm
EUV
EUV
1980
1990
2000
2010
2020
Source Borkar et al., GVLSI 2002 Grobman, DAC
2001
8
Optical Proximity Effects/Correction

• OPC is effective but very complex

Original Layout 0.18 mm
Silicon Image
Silicon Image With OPC
OPCLayout
Image from Pati, DAC99
9
OPE/OPC Example
Image from B. Cory, nVidia
10
Etc.

• Overall static variability is on the rise

From S. Nassif, ISPD 2004
11
Impact of Static Variability
Frequency 30 Leakage Power 5-10X
From Borkar et al., GVLSI 2002
12
Dynamic Variability

• Voltage
• Activity change
• Power deliveryRLC
• Dynamicns to 10-100 mSec
• Within die
• Temperature
• Change in activity and ambient
• Dynamic 100s of mSec to mSec
• Within die

13
Temperature Profile Example

• Varies spatially and with time (switching
  activity)

From C. Visweswariah, IBM
14
Design Process Changes Due to Variability
System
From R.Puri, IBM
Logic
Circuit
Deterministic
Layout
Models
Manu-facturing
Characterization
15
Variability and Design
Chip behavior in the face of environmental and
manufacturing variations
Critical area Voronoi diagrams Redundant via
insertion Wire bending/spacing
Statistical timing Yield prediction Design
centering Design for manufacturability
From C. Visweswariah, IBM
16
Design versus Reality
Reality Check?
Reality Check?
17
Why Better Resolution from Product Test?

• Yield limiters may be deeply buried inside the
  product design
• Very context-sensitive and design specific
• Non-visual and not represented in test vehicles

WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
18
The New Role of Test

• Test may be the first real opportunity to uncover
  the statistical impact of new catastrophic and
  parametric defect sources
• Test can become a key tool for statistical design
  verification and design/yield learning

19
Defect/Design Learning fromElectrical Test

• Dr. Bernd Koenemann
• Mentor Graphics Corporation

20
Agenda

• Part I
• Introduction
• Defects and Technology Challenges
• Part II
• Defect Learning
• Background
• Enhanced Learning with Test
• Total Analysis Vision
• Summary

21
Part II
22
The New Role of Test

• Test may be the first real opportunity to uncover
  the statistical impact of new catastrophic and
  parametric defect sources
• Test can become a key tool for statistical design
  verification and design/yield learning

23
Adaptation of Test
Realistic
Wafer/chips
Faults
Test
ATPG/Fault-Grading
Low Cost
ShippedProducts
TestFails
24
Parametric Constraints Timing

• Have to deal with defects and process variability
• Test edge placement limited by tester accuracy

Conceptual Arrival Time and Defect Distribution
for a Delay Path
f(d)
Requ. Arrival Time
d
nom.
1
2
-1
-2
25
At-Speed Test With On-Chip PLL

• ATE controlled scan loading (i.e. slow shift)
• On-chip PLL controlled launch capture

26
Targeted Detection

• E.g., defect-based approach
• Note may skip circuit simulation for some fault
  types

27
Auxiliary Coverage Metrics

• Relate detection to some test set properties
• E.g., n-detect profile of stuck-at tests

35
Individual
100
Fallout
30
91
25
Cumulative Fallout Ratio
59
76
20
Failed Devices
15
10
5
0
2nd Detect
3rd Detect
4th Detect
5th Detect
Pattern Set
From B.Benware et al., LSI Logic, Mentor Graphics
28
Low Cost Scan Test Compression

• High Test Quality
• No loss in test coverage compared to normal scan
• Support for all fault/pattern types
• Stuck-at, transition, path delay,
  multiple-detect, IDDQ, bridging, etc.
• Combinational, sequential, multi-load, etc.
• Compression of test time and/or test data volume
• Low overhead (gate count, placement/wiring,
  power, timing, etc.)
• Minimal impact to functional logic design
• Minimal performance impact

29
On-Chip Test Compression

• Uses ATPG
• X-state handling
• Change design
• Masking
• X-tolerant compaction
• Diagnostics
• Bypass mode
• Direct diagnostics (no bypass needed)

Decompressor
Compactor
Chip
CompressedStimuli
CompactedResponses
ATE
30
Defect Learning

• Background
• Inspection/metrology
• Test/characterization Vehicles
• Yield management systems
• Enhanced learning with test
• Debug/diagnostics/failure-analysis
• Statistical processing

31
Inspection/Metrology

• Scanning for visible defects (mask/wafer)
• Special equipment
• Creates defect maps
• Measurement/tracking of process parameters
• Metrology equipment for specific process issues
  (e.g., surface planarity, oxide thickness, etc.)
• Equipment logs
• Measurement of circuit parameters
• Scribe-line (KERF) monitors
• Dedicated monitor structures
• On-chip monitors (e.g., PSRO, etc.)

32
In-Line Inspection (Surface Scan)
Equipment
Results File
e.g., Defect x-y-coordinates Defect size Defect
classification Etc.
Detailed Image
Wafer Map Image
From Multiple Sources
33
In-Line Inspection Characteristics

• Visualizes defects
• Defect densities
• Spatial distributions
• Time-consuming
• Limited subset of wafers/layers/process steps
• No immediate indication of yield impact if defect
  density is within expectations
• Limited scope
• Not all defects are visible
• Significance of non-visible defects is growing
  (ITRS)

34
Test Vehicles

• Simple monitor structures for specific defect
  types
• E.g., metallization, vias, contacts, etc.
• Sophisticated design/process characterization
  monitors
• E.g., multiple defect types, representative of
  design/library elements, etc.

35
Simple Serpentine Test Structure

• For measuring metallization defect densities

From Hess, et al., 2001
36
Sophisticated Test Vehicles

• Combination of multiple monitor structures
• Targeting random and feature-based defects
• Integrated into comprehensive characterization
  flow

From PDF Solutions
37
Test Vehicle Characteristics

• Extract defect densities and yield sensitivities
• Multiple defect categories
• Representative circuit structures can reveal
  impact of defects on electrical fails
• Costly
• Dedicated designs that must be processed through
  line
• Design time, limited runs, etc.
• Limited scope
• Only detect/measure defect rates related to the
  circuit structures provided in the test vehicle
• May or may not include all yield-sensitive
  features found in real product designs

38
Yield Management Systems

• Infrastructure for monitoring and analyzing yield
  issues
• Data collection
• Data warehousing
• Data mining/analysis
• Increasingly comprehensive
• Many data types (e.g., logistics, equipment,
  metrology, binning, etc.)
• Many analysis routines (e.g., queries, report
  generation, visualization, alert automation,
  etc.)
• Customizable (e.g., database extensions,
  scripting/APIs, etc.)

39
Example E-Diagnostics Infrastructure
From Kot and Yedatore, Semi International, 2003
40
Example Visualization (Test)
Source, R. Madge, ITC 2004
41
Yield Management Systems Characteristics

• Very comprehensive
• Logistics, equipment, events, metrology, binning,
  etc.
• Can enable fast problem detection/correction
• Available and flexible
• Offered by multiple vendors
• Extendible data bases, queries, analyses,
  visualizations
• Limited scope
• May not have access to intra-chip design data
• Analysis resolution primarily at wafer-map level
• Extending resolution to intra-chip design/process
  interactions generally requires home-grown
  add-ons (happening in several places)

42
Diagnostics

• Finding the root-cause of a particular test fail
• Characterizing the failing behavior
• Localizing the most likely problem area
• Integral part of
• Silicon debug
• Failure analysis

43
Flow/Equipment/Tools for Silicon Debug
Production Tester and/or Validation System
Detect a Fault (Test, Fault Detection)
Engineering Tester, Temperature Control Unit
(TCU)
Characterize the Fault (Fault Characterization)
Engineering Tester, Prober, CAD Nav, TCU
Internally Isolate the Fault (Fault Isolation)
Simulation, Debug SW Tools, Engineering Tester,
Prober, TCU
Determine Design Flaw (Bug Identification or
Root Cause)
Simulation, Design Tools, FIB, CAD Nav, Prep
Tools
Fix the Bug (Engineering Change Order)
Verify the Fix (Design Verification)
FIB, CAD Nav, Prep Tools Design Verification Tools
From S. Maher
44
Example Equipment of the Trade
Source Credence/NPTest
45
Example Time-Resolved Backside Imaging
.13mm Inverter Chain Image . 2mm Image
Resolution (Through Si Backside)
Source Credence/NPTest
46
Memories

• Memories are relatively easy to diagnose
• Regular logic structures (word, bit)
• Regular physical structures (row, column)
• Bitmapping (i.e., logging the failing logic
  words/bits) is supported by Automatic Test
  Equipment (ATE) and Built-In Self-Test (BIST)
• Stand-alone and embedded memories in product
  chips have been and are important defect learning
  vehicles

47
Memory Diagnostics

• Log fail bitmaps from ATE/BIST
• Convert logical maps to physical maps
• Requires access to physical design structure
• Visualize/analyze logical/physical fail bit maps
• Look for characteristic patterns (e.g.,
  single-bit fail, row/column fail, etc.)
• Overlay with other data, e.g.,
• Layout (GDS II)
• Defect maps from in-line inspection
• Requires reticle/wafer map for coordinate
  translation
• Initiate Failure Analysis (FA)

48
Physical Memory Fail Bitmap Examples
Vertical PairBit Line Contact
Partial ColumnResistive Bit Line Short
Multi-RowAddress Decoder
SwatchCMP Scratch
Entire BitSense amp, I/O
CatastrophicTiming Circuit
From R. Aitken, ARM/Artisan
49
Overlay of Bitmap and Defect Map
50
Logic

• Logic is more difficult to diagnose
• Non-regular
• Limited visibility of internal circuit states (no
  equivalent to direct bitmapping as for memories)
• Traditionally has been a time-consuming manual
  effort
• Significant automation possible for designs with
  scan
• Enhanced state visibility at scan cells and
  primary outputs
• However, still no direct mapping of logic outside
  scan cells
• Failing scan cells may not be actual problem
  locations

51
Example
From A. Weber, Semi International, 2004
52
Logic Diagnostics (with Scan)

• Log some number of fail sets (failing scan cells
  and primary outputs) from ATE or BIST
• Run logic fault isolation software
• Create gate-level callouts (net/pin names, fail
  type) most likely near the problem area
• Visualize callouts in layout
• Requires link between gate-level netlist and
  layout (e.g., from running LVS)
• Overlay callouts with defect maps or other
  information
• Requires translation to/from wafer-level
  coordinates
• Initiate Failure Analysis (FA)

53
Diagnostic Flow for FA
DesignDB
Netlist
FailSets
Run Test withFail DataCollection
Logic Fault Isolation
Determine Failing Net Location
Visualize Failing Net
IdentifyDie ofInterest
NavigatetoLocation
Determine Cause of Failure
From D. Abercrombie
54
Fault Localization Software
ATE/BIST
Fail sets
TestPatterns
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
55
Callout Example
Note from IBM TestBench
56
Overlay with Defects(Logic Bitmapping)
Fail Net Visualization
Note from LSI Logic
57
Statistical Diagnostics for Logic

• Emerging defect/yield learning method for complex
  logic designs
• Implement comprehensive fail set logging for
  initial ramp and for volume production test
• Run logic fault isolation on many/all fail sets
  (could be thousands per day)
• Write all callout information into database
• Statistically sort, analyze, and visualize the
  cumulative callout information, e.g.,
• Query by cell-type, cell-instance/location, etc.
• Stack results on chip layout, reticle, and/or
  wafer map
• Compare with yield predictions
• Etc.

58
Example Stacked Callout Visualization
Note from LSI Logic
59
Example Sorting by Cell Type
Relative occurrencenormalized to occupied area
60
50
40
30
20
10
0
NOR
Buffer
Inverter
AND-OR
Flip-Flop
Multiplexer
FromD. Apello, et al., ST Micro
60
Example Sorting by Cell Instance/Location

• Statistical analysis of single-net failures

Cell a
Cell b
Cell c
Cell d
Cell e
Probability
From D. Appello, et al., ST Micro, Synopsys
61
Underlying Problem
FromD. Appello, et al., ST Micro, Synopsys
62
State of the Art

• Statistical diagnostics of logic fails are a
  rapidly emerging design/defect learning
  technology
• Learning design-specific issues from product
  chips
• Statistical relevance with large number of
  samples
• Complement/enhance existing fab-oriented yield
  management systems
• Add intra-chip resolution and visibility
• Complement/enhance DFM and yield modeling
• Provide feedback and calibration
• Most existing solutions are home-grown at IDMs
• Challenging data security/access issue for
  fabless/foundry
• No integrated commercial solution yet

63
Conclusion Vision of an Integrated Solution
Debug/FA Lab
Yield Management
Applications
Applications
APIs/Utilities
APIs/Utilities
Design Database
Data Warehouse
WIP, Metrology, Test,
Design, design analysis,
Inspection, etc.
design intent, etc.
64
Flow
ATPG Patterns
Fail Data
Suspect Nets,Fail Behavior
Single SuspectDisplay
DesignBrowsing/Navigation/Visualization
ATPG
detailed FaultLocalization volume
ATE
Failure Analysis
SampleSelection
Multi SuspectsDisplay
DefectIdentification
Yield Analysis Software Tool End Users Yield
Engineers Product Engineers Manufacturing
Engineers Design Engineers Test Engineers
Manufacturing Data Warehouse
WIP Data
Image Data
Metrology Data
Yield Analysis Software
65
The End