CHAPTERS 7

1
CHAPTERS 7 8

• NETWORKS 1 ECE 09.201.01
• 17 October 2006 Lecture 11
• ROWAN UNIVERSITY
• College of Engineering
• Dr Peter Mark Jansson, PP PE
• DEPARTMENT OF ELECTRICAL COMPUTER ENGINEERING
• Autumn Semester 2006 Quarter One

2
admin

• next Tuesday Lab Period (3.15-6 PM)
• In Rowan Hall Auditorium
• Final Test (3) in Networks 1
• HW 7 due as Part of Final Test (10)
• But must be turned in at 9.25 AM class

3
networks I

• Todays learning objectives
• More on RC or RL circuits
• Initial conditions of switched circuits
• First (1st) order circuits

4
Handier Charts for studying

• see Table 7.8-1
• Characteristics of Energy Storage Elements
• Page 275
• and Table 7.13-2
• Parallel and Series Capacitors and Inductors
• Page 291
• Inductance
• Behaves as a short to constant DC current
• Capacitance
• Behaves as an open circuit to constant DC voltage

5
Table 7.8-1 (p. 275) Characteristics of Energy
Storage Elements
6
Initial conditions of switched circuits

• switch changes
• t0, at time of switching
• t0-, just prior to switching
• t0, just after switching
• t8, a long time after switching, steady state
• Instantaneously
• Capacitor current can change, its voltage can
  not
• Inductor voltage can change, its current can not

7

• steady state circuit conditions just before the
  switching change and again a very long period
  after the switching change
• inductor in a steady DC current acts as a short
  circuit with no voltage drop
• vL L (di/dt) if di/dt0 so does v
• capacitor in a constant DC voltage acts as an
  open circuit with no current flow
• iC C (dv/dt) if dv/dt0 so does i

8
simple illustrations of switching

• an inductor example
• LC1 If R1R21? What is i1 and iL at t(0-)
  t(0)
• a capacitor and inductor example
• LC2 What is vC and iL at t(0-) t(0)

9
HW problem 7.8-2

• page 300

LC3 What is total resistance the 12V source sees
in the circuit at t(0-) t(0), answer is two
(2) numbers Rt(0-) Rt(0),
10
Circuit for Example 7.8-1(page 277) Switch 1
closes at t 0 and switch 2 opens at t 0,
Find iL(0), vc(0), dVc(0)/dt, and diL(0)/dt,
assume switch 2 has been closed for a long time.
11
Circuit for Example 7.8-1 at t(0-) Switch 1 is
not closed yet, and switch 2 has been closed for
a long time, all current flows through 1?
resistor. Find iL(0-) and voltage across
capacitor vc(0-) is ?
Show your answers as Learning check 4
12
Once you found out what iL(0-) and voltage across
capacitor vc(0-) is, how do these quantities
relate to

• The instant afterwards?
• iL(0-) and iL(0) current in inductor
• vc(0-) and vc(0) voltage across capacitor
• why?

Show your answers as Learning check 5
13
Circuit for Example 7.8-1 at t(0) Switch 1 has
just closed, and switch 2 has just opened. To
solve for diL(0)/dt we need a KVL in right hand
mesh, to solve for dvc(0)/dt we need a KCL at
node a.
KVL in right hand mesh vL vC 1iL 0 so
since vL L(diL(0)/dt) vL vC -1iL -2 0
-2V THEN -2 LdiL(0)/dt -2A/s diL(0)/dt
KCL at node a (vc-10)/2 ic iL 0 so
ic(0)6-06A THEN dvc(0)/dt ic(0)/C
6/(1/2) 12V/s
14
What did we learn here?

• at switching time (t0) current in inductor and
  voltage in capacitor remained constant
• but voltage in inductor changed instantaneously
  from 0V to -2V with diL(0)/dt -2A/s
• and
• current through capacitor changed instantaneously
  from 0 to 6 A with
• dvc(0)/dt 12V/s

15
remember

• Inductance
• Behaves as a short to constant DC current
• Capacitance
• Behaves as an open circuit to constant DC voltage

16
IMPORTANT CONCEPTS FROM CH. 7

• I/V Characteristics of C L.
• Energy storage in C L.
• Writing KCL KVL for circuits with C L.
• Solving op-amp circuits with C or L in feedback
  loop.
• Solving op-amp circuits with C or L at the
  input.

17
new concepts from ch. 8

• response of first-order circuits
• to a constant input
• the complete response
• stability of first order circuits
• response of first-order circuits
• to a nonconstant (sinusoidal) source

18
What does First Order mean?

• circuits that contain capacitors and inductors
  can be defined by differential equations
• circuits with ONLY ONE capacitor OR ONLY ONE
  inductor can be defined by a first order
  differential equation
• such circuits are called First Order Circuits

19
whats the complete response (CR)?

• Complete response transient response steady
  state response
• OR.
• Complete response natural response forced
  response

20
finding the CR of 1st Order Circuit

• Find the forced response before the disturbance.
  Evaluate at t t(0-) to determine initial
  conditions v(0-) or i(0-)
• Find forced response (steady state) after the
  disturbance t t(8) Voc or Isc
• Add the natural response (Ke-t/?) to the new
  forced response. Use initial conditions to
  calculate K

21
Figure 8.2-1 (p. 306)A plan for analyzing
first-order circuits. (a) First, separate the
energy storage element from the rest of the
circuit. (b) Next, replace the circuit connected
to a capacitor by its Thévenin equivalent
circuit, or replace the circuit connected to an
inductor by its Norton equivalent circuit.
22
RC and RL circuits

• RC circuit complete response
• RL circuit complete response

23
simplifying for analysis

• Using Thevenin and Norton Equivalent circuits
  can greatly simplify the analysis of first order
  circuits
• We use a Thevenin with a Capacitor
• and a Norton with an Inductor

24
Thevenin Equivalent at t0
i(t)
-
25
Norton equivalent at t0
26
1st ORDER CIRCUITS WITH CONSTANT INPUT
27
Example (before switch closes)

• If vs 4V, R1 20k?,
• R2 20 k?
• R3 40 k?
• What is v(0-) ?

LC6 Write down v(t) at t(0-) t(0)
28
as the switch closes

• THREE PERIODS emerge..
• 1. system change (switch closure)
• 2. (immediately after) capacitor or inductor in
  system will store / release energy (adjust and/or
  oscillate) as system moves its new level of
  steady state (a.k.a. transient or natural
  response) . WHY???
• 3. new steady state is then achieved (a.k.a. the
  forced response)

29
Thevenin Equivalent at t0
i(t)
-
KVL
30
SOLUTION OF 1st ORDER EQUATION
31
SOLUTION CONTINUED
32
SOLUTION CONTINUED
33
so complete response is

• complete response v(t)
• forced response (steady state) Voc
• natural response (transient)
• (v(0-) Voc) e -t/RtC)
• NOTE ? RtC

34
Figure 8.3-1 (a) A first-order circuit and (b) an
equivalent circuit that is valid after the switch
opens. (c) A plot of the complete response.
LC7 What is Rt(0) and VOC?
35
Lets Build the Complete Response for the circuit
1) Find the forced response before the
disturbance. Evaluate at t t(0-) to determine
initial conditions v(0-) or i(0-) in our case
v(0-) 2V 2) Find forced response (steady
state) after the disturbance t t(8) Voc or
Isc in our case VOC 8V 3) Add the natural
response (Ke-t/?) to the new forced response. Use
initial conditions to calculate K in our case Rt
10,000 and C2?F so RtC has value of 20 and
units of milliseconds
t in units of milliseconds
36
What is meaning of this new equation?

• Lets plot a few points.

LC8 When does steady state occur With respect to
RtC?
37
WITH AN INDUCTOR
t 0
R1
R2
R3
i(t)
L
vs
Why ?
LC9 Give your answer
38
Norton equivalent at t0
Why ?
KCL
39
SOLUTION
40
so complete response is

• complete response i(t)
• forced response (steady state) Isc
• natural response (transient)
• (i(0-) isc) e t(Rt/L))
• NOTE ? L/Rt

41
Figure 8.3-2(a) A first-order circuit and (b) an
equivalent circuit that is valid after the switch
closes. (c) A plot of the complete response.
42
Figure E8.3-1 (p. 321)
43
Figure E8.3-2 (p. 322)
44
Stability of 1st order circuits

• when ?gt0 the natural response vanishes as t ?8
• THIS IS A STABLE CIRCUIT
• when ?lt0 the natural response grows without bound
  as t?8
• THIS IS AN UNSTABLE CIRCUIT

45
forced response summary
46
Unit step or pulse signal

• vo(t) A Be-at
• for t gt t0, and vo(t) 0 before

47
Example

• 8.6-2, p. 333

48
Figure 8.6-12 (p. 333) The circuit considered
in Example 8.6-2
49
Figure 8.6-13 (p. 333) Circuits used to
calculate the steady-state response (a) before t
0 and (b) after t 0.
50
HANDY CHART
ELEMENT CURRENT VOLTAGE
51
IMPORTANT CONCEPTS FROM CHAPTER 8

• determining Initial Conditions
• determining T or N equivalent to simplify
• setting up differential equations
• solving for v(t) or i(t)

52
Dont forget HW 7

• due next Tuesday

53
Assignment 7 due next Tuesday

• Assignment 7
• Due Tuesday, October 17, 2006-925 AM
• Chapter 7 - Pages 294-303    Problems 7.4-3,
  7.4-5, 7.5-2, 7.5-3, 7.6-2, 7.7-1, 7.7-3, 7.8-1,
  7.8-3, 7.9-2, DP 7-5
• Chapter 8 - Pages 349-362    Problems  8.3-1,
  8.3-5, 8.3-8, 8.3-9, 8.3-10, 8.4-4, 8.4-6, 8.6-2,
  8.6-6, 8.9-1, 8.9-2, 8.9-3    Verification
  Problems VP 8-1, VP8-2, VP 8-3    Design
  Problems  DP 8-1, DP 8-2