Design and Implementation of VLSI Systems

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Design and Implementation of VLSI
Systems (EN0160) Lecture 34 Design Methods
(beyond Tanner Tools)
Prof. Sherief Reda Division of Engineering, Brown
University Spring 2007
sources Weste/Addison Wesley Maxfield/Newnes
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Stage I. IC Design, Verification, and Test
Ideas
Specification
simulation/ verification
Design
C-based design (SystemC)
schematics
HDL (Verilog/VHDL)
Test-structure Insertion
library
Synthesis
gate-level design
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Stage II. IC Physical Implementation Flow
Custom/Application Specific IC (ASIC)
gate-level circuit
Floorplanning/placement
repeater insertion
clock tree synthesis
P/G network / routing
metal fill insertion
DRC/LVS
mask generation / OPC
reticles/masks
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Stage III. Fabrication and Packaging
reticles
fabricate wafer
Test dies
dice and package the good ones
chips
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Stage I. IC Design, Verification, and Test
Ideas
Specification
Design
verification
C-based design (SystemC)
schematics
HDL (Verilog/VHDL)
Test-structure Insertion
Library
Synthesis
gate-level design
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Design Entry
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Functional Simulation
Make sure your design is logically correct.
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Synthesis
Synthesis transforms HDL to gates
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Verification

• We cannot try all possible input combinations to
  check our design
• How can we verify that our synthesizer is
  correct?
• Imagine you are designing a traffic light
  controller, how can you guarantee that the light
  will not be simultaneously green for both
  directions?
• Formal verification uses mathematical techniques
  to verify certain properties of your design.

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Stage II. IC Physical Implementation Flow
Custom/Application Specific IC (ASIC)
gate-level circuit
Floorplanning/placement
repeater insertion
clock tree synthesis
P/G network / routing
metal fill insertion
DRC/LVS
mask generation / OPC
reticles/masks
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Fast timing analysis using static timing analysis
(STA)
C17 from ISCAS85 benchmarks
I1
O1
I2
I3
I4
O2
I5
I6

• What is the worst delay of this circuit without
  regard to the dynamic input patterns?
• What are the critical path(s) that lead to this
  delay? ? perhaps timing can be improved if we
  adjust them

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Floorplanning and placement
Floorplanning (chip outlining) is a small scale
2-D assignment problem ? determines positions
for large blocks of logic/memory
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Clock tree synthesis

• Clock net(s) ? delivers the periodic generated
  clock signal to FFs
• Design objectives
• Zero-or prescribed skew
• minimum wirelength
• minimize buffers for signal integrity

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Buffering (repeater insertion) for timing and
signal integrity
The situation is complicated in case of multi-pin
nets
sink
source
sink
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Design and analysis of power supply networks
Blaauw et al., DAC98

• Power supply network delivers Vdd/Gnd signals to
  all components.
• Main challenges
• 1. IR drop voltage at delivery point is degraded
  than the ideal voltage
• performance drop
• signal integrity problems
• 2. electromigration

PowerPC 750 power grid
PowerPC 750 IR-drop map
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Routing

• Objective determine routes (tracks, layers, and
  vias) for each net such that the total wirelength
  is minimized.
• Be careful with routing critical nets and clock
  nets

pin p1
congestion
cell
pin p2
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Routing and parasitic extraction

• Multi-pin nets add more complexity in routing

sink
source
sink

• After all routes are determined, you can
  calculate the parasitic capacitance between each
  wire and its neighbors

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Fill insertion

• CMP (chemical mechanical polishing) is executed
  for each layer before buildup of other layers
• Remember the DRC violations from L-Edit! How can
  metal fill insertion helps in smoothing surfaces?

(animation is not technically correct! Photos
are form Quirk/Serda
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Mask preparation and resolution enhancement
techniques (RET)
original layout
GDSII
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Mask preparation and resolution enhancement
techniques (RET)
Light source 193nm
130nm feature
Schellenberg, IEEE Spectrum03
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Stage III. Fabrication and Packaging
reticles
fabricate wafer
Test dies
dice and package the good ones
chips
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Fabrication and Test

• Testing
• Functional (yield)
• How many circuits work (have no defects)?
• Delay/Power (parametric yield)
• What is the speed and power of the ones that work?

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Dicing and packaging
reticles
dice
wafer
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Packaging choices
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Summary

• Overview of IC design flow
• We are done with main lectures
• We meet in exactly one week on May 4th to give
  your project presentations