Chapter 2 MOS Transistor Theory

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Chapter 2 MOS Transistor Theory
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Outline

• MOS Capacitor
• nMOS I-V Characteristics
• pMOS I-V Characteristics
• Second Order Effects
• Gate and Diffusion Capacitance
• RC Delay Models
• Good Reference Operation and Modeling of the
  MOS transistor by Yannis Tsividis is an
  excellent book covering MOS Transistor theory

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Capacitance

• Any two conductors separated by an insulator have
  capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion (or depletion )capacitance
  because it is associated with source/drain
  diffusion.
• Parasitic or undesirable capacitances

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Gate Capacitance

• Approximate channel as connected to source
• Cgs Cg eoxWL/tox CoxWL CpermicronW
• Cpermicron is typically about 1.5-2 fF/mm

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Diffusion Capacitance

• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
• Use small diffusion nodes
• Comparable to Cg
• for contacted diff
• ½ Cg for uncontacted
• Varies with process

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Effective Resistance

• Shockley models have limited value
• Not accurate enough for modern transistors
• Too complicated for much hand analysis
• Simplification treat transistor as resistor
• Replace Ids(Vds, Vgs) with effective resistance R
• Ids Vds/R
• R averaged across switching of digital gate
• Too inaccurate to predict current at any given
  time
• But good enough to predict RC delay

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RC Delay Model

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width
• Resistance inversely proportional to width

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RC Values

• Capacitance
• C Cg Cs Cd 2 fF/mm of gate width
• Values similar across many processes
• Resistance
• Improves with shorter channel lengths
• Unit transistors
• Defined as a minimum contacted device (4/2 l)

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

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Inverter Delay Estimate

• Estimate the delay of a fanout-of-1 inverter

d 6RC
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DC Transient Response
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Outline

• DC Response
• Logic Levels and Noise Margins
• Transient Response
• Delay Estimation

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

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Activity

• 1)     If the width of a transistor increases,
  the current will 
• increase decrease not change 
• 2)     If the length of a transistor increases,
  the current will
• increase decrease not change
• 3)     If the supply voltage of a chip increases,
  the maximum transistor current will
• increase decrease not change
• 4)     If the width of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 5)     If the length of a transistor increases,
  its gate capacitance will
• increase decrease not change
• 6)     If the supply voltage of a chip increases,
  the gate capacitance of each transistor will
• increase decrease not change

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DC Response

• DC Response Vout vs. Vin for a gate
• Ex Inverter
• When Vin 0 -gt Vout VDD
• When Vin VDD -gt Vout 0
• In between, Vout depends on
• transistor size and current
• By KCL, must settle such that
• Idsn Idsp
• We could solve equations
• But graphical solution gives more insight

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Transistor Operation

• Current depends on region of transistor behavior
• For what Vin and Vout are nMOS and pMOS in
• Cutoff?
• Linear?
• Saturation?

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nMOS Operation
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nMOS Operation
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nMOS Operation
Vgsn Vin Vdsn Vout
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nMOS Operation
Vgsn Vin Vdsn Vout
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pMOS Operation
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pMOS Operation
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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pMOS Operation
Vgsp Vin - VDD Vdsp Vout - VDD
Vtp lt 0
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I-V Characteristics

• Make pMOS wider than nMOS such that bn bp

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Current vs. Vout, Vin
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Load Line Analysis

• For a given Vin
• Plot Idsn, Idsp vs. Vout
• Vout must be where currents are equal in

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Load Line Analysis

• Vin 0

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Load Line Analysis

• Vin 0.2VDD

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Load Line Analysis

• Vin 0.4VDD

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Load Line Analysis

• Vin 0.6VDD

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Load Line Analysis

• Vin 0.8VDD

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Load Line Analysis

• Vin VDD

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Load Line Summary
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DC Transfer Curve

• Transcribe points onto Vin vs. Vout plot

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Operating Regions

• Revisit transistor operating regions

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Operating Regions

• Revisit transistor operating regions

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Beta Ratio

• If bp / bn ? 1, switching point will move from
  VDD/2
• Called skewed gate
• Other gates collapse into equivalent inverter

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Noise Margins

• How much noise can a gate input see before it
  does not recognize the input?

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Logic Levels

• To maximize noise margins, select logic levels at
  
• unity gain point of DC transfer characteristic

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Transient Response

• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
  changes
• Requires solving differential equations
• Input is usually considered to be a step or ramp
• From 0 to VDD or vice versa

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Inverter Step Response

• Ex find step response of inverter driving load
  cap

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Delay Definitions

• tpdr rising propagation delay
• From input to rising output crossing VDD/2
• tpdf falling propagation delay
• From input to falling output crossing VDD/2
• tpd average propagation delay
• tpd (tpdr tpdf)/2
• tr rise time
• From output crossing 0.2 VDD to 0.8 VDD
• tf fall time
• From output crossing 0.8 VDD to 0.2 VDD

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Delay Definitions

• tcdr rising contamination delay
• From input to rising output crossing VDD/2
• tcdf falling contamination delay
• From input to falling output crossing VDD/2
• tcd average contamination delay
• tpd (tcdr tcdf)/2
• tpd (propogation delay) is the MAXIMUM time and
  tcd is the MINIMUM time from the input 50
  crossing to the ouput 50 crossing

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Simulated Inverter Delay

• Solving differential equations by hand is too
  hard
• SPICE simulator solves the equations numerically
• Uses more accurate I-V models too!
• But simulations take time to write

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Delay Estimation

• We would like to be able to easily estimate delay
• Not as accurate as simulation
• But easier to ask What if?
• The step response usually looks like a 1st order
  RC response with a decaying exponential.
• Use RC delay models to estimate delay
• C total capacitance on output node (load)
• Use driver effective resistance R
• So that tpd RC
• Characterize transistors by finding their
  effective R
• Depends on average current as gate switches

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RC Delay Models

• Use equivalent circuits for MOS transistors
• Ideal switch capacitance and ON resistance
• Unit nMOS has resistance R, capacitance C
• Unit pMOS has resistance 2R, capacitance C
• Capacitance proportional to width with constant L
• Resistance inversely proportional to width

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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Example 3-input NAND

• Sketch a 3-input NAND with transistor widths
  chosen to achieve effective rise and fall
  resistances equal to a unit inverter (R).

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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3-input NAND Caps

• Annotate the 3-input NAND gate with gate and
  diffusion capacitance.

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Elmore Delay

• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder

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Example 2-input NAND

• Estimate worst-case rising and falling delay of
  2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Example 2-input NAND

• Estimate rising and falling propagation delays of
  a 2-input NAND driving h identical gates.

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Delay Components

• Delay has two parts
• Parasitic delay
• 6 or 7 RC
• Independent of load
• Effort delay
• 4h RC
• Proportional to load capacitance

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Contamination Delay

• Best-case (contamination) delay can be
  substantially less than propagation delay.
• Ex If both inputs fall simultaneously

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Diffusion Capacitance

• we assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex NAND3 layout shares one diffusion contact
• Reduces output capacitance by 2C
• Merged uncontacted diffusion might help too

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Layout Comparison

• Which layout is better?