Chapter 3 - Digital Logic

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Chapter 3 - Digital Logic
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History of the Transistor
The Transistor

• Around 1945, Bell Labs scientists discovered that
  silicon was comprised of two distinct regions
  differentiated by the way in which they favored
  current flow.
• The area that favored positive current flow they
  named "p" and the area that favored negative
  current flow they named "n".
• The transistor effect describes the change from a
  condition of conductivity (switched on, full
  current flow) to a condition of insulation
  (switched off, no current flow).

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Digital Logic Circuits
The Transistor

• Computers large number of simple structures
• Intel 4004 2,300 transistors
• Intel Pentium 4 42 million transistors
• Intel Core 2 Duo 291 million transistors
• Intel i7 Bloomfield 731 million transistors

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Moores Law
The Transistor
2010s
Moores Law The number of transistors per area
doubles every 1.5 - 2 years.
Early 1900s
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The MOS Transistor
The Transistor

• A transistor acts like a switch
• Conducts current when "ON"
• No current flow when "OFF"

MOS metal-oxide semiconductorCMOS
complementary MOS with both N and P transistors
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The Transistor
Field Effect Transistor
N Type
P Type
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CMOS Gates
The Transistor
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• Complementary pull-up / pull-down logic
• pull-down is " ON" when pull-up is "OFF "
• and vise versa.

Pull-up Structure (P-Type)
Source
Complementary
Pull-down Structure (N-Type)
The C in CMOS
Even in the digital world, "EVERYTHING IS
ANALOG"!
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The Inverter
Digital Logic Devices
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The NOR Gate (NOT-OR)
Digital Logic Devices
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The OR Gate
Digital Logic Devices

• How do you build an OR gate?

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The NAND Gate (NOT-AND)
Digital Logic Devices
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The AND Gate
Digital Logic Devices

• How do you build an AND gate?

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Complementary Logic
Digital Logic Devices
Which of these examples is an inverter?
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Drivers
Digital Logic Devices

• Why cant complementary logic connect to a bus?

• A 0 and a 1 on the bus would let the magic smoke
  out!
• Solution Tri-state driver

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Notation
Notation and Precedence

• Logical operator notation (in order of
  precedence)
• NOT, bar, circle, ,
• AND, , ?, ?
• OR, , ?
• Examples

y NOT(s) AND a AND NOT(b)
y (s ? a ? b) (s ? a ? b)
(x ? y) x ? y
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De Morgans Law
De Morgans Law
To distribute the bar, change the operation.
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De Morgans Proof
De Morgans Law
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Reading Functions from Symbols
Translations
The output will be high if any of the inputs are
low...
The output will be low if all of the inputs are
high...
a b out 0 0 1 0 1 1 1 0 1 1 1 0
The output will be high if the first input is
low OR the second input is high...
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You Should Know How to Translate
Translations
LogicEquations
These are three different ways of representing
logical information
You can convert any one of them to any other
LogicGates
TruthTables
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Gates ? Equations
Translations

• Equations to Gates

y NOT(s) AND a AND NOT(b)

• Gates to Equations

(s ? a ? b)
(s ? a ? b)
(s ? a ? b)
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Equations ? Truth Tables
Translations

• Truth table to equations

Each row of truth table is an AND gate Each
output column is an OR gate
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Truth Tables ? Gates
Translations

• Truth table to Gates

Each row of truth table is an AND gate Each
output column is an OR gate
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Manipulating Logic Expressions
Translations
Laws (basic identities) of Boolean algebra.
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Quiz
Quiz

• What is the logical equation and truth table for
  the following circuit?

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Decoders
Circuits

• Decode the input and signify its value by raising
  just one of its outputs.

1 if A,B 00
1 if A,B 01
A B W X Y Z 0 0 0 1 1 0 1 1
1 if A,B 10
1 0 0 0
0 1 0 0
1 if A,B 11
0 0 1 0
0 0 0 1
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Multiplexors
Circuits

• Connect one of its inputs to its output according
  to select signals
• Useful for selecting one from a collection of
  data inputs.
• Usually has 2n inputs and n select lines.

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Adders
Circuits

• At each digit position add together the 2
  operands and the carry-in

a0
b0
a1
b1
a2
b2
a3
b3
c 0110 0101 1011
Full Adder
Full Adder
Full Adder
Full Adder
0
c0
c1
c2
c3
s0
s1
s2
s3
Just like longhand addition except its in
binary...
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Full Adder Module Design
Circuits
a b c cyout sum 0 0 0 0 0 0 0 1 0
1 0 1 0 0 1 0 1 1 1 0 1 0 0
0 1 1 0 1 1 0 1 1 0 1 0 1 1
1 1 1
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Programmable Logic Arrays
PLAs

• Programmable Logic Array (PLA) can be used to
  implement any logic function

• Take truth table of any logic function
• Convert into equation (any truth table can be
  expressed as set of and expressions ored
  together)
• PLA programmed by making/breaking wire connections

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PLA Example
PLAs
Out2 ABC ABC ABC
Out3 ABC ABC
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Logical Completeness
Logical Completeness

• What is the minimum set of gate types needed to
  implement any logic function?

• AND gate, OR gate, Inverter

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Logical Completeness
Logical Completeness
NAND (by itself) is logically complete if you can
implement an INVERTER, AND, and OR gate using
only NAND gates.

• NAND
• INVERTER
• AND
• OR

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Storage Elements
Sequential Logic

• Everything so far has been combinational logic
• the output is strictly a function of the current
  inputs
• Computing systems need storage elements
• for holding previously computed values
• for saving state
• Two types of locks

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Bi-Stability Key to Memory
Sequential Logic

• When there are 2 stable states - a bi-stable
  circuit
• RS Latch

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Sequential Logic
RS Latch Bi-Stable Circuit
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Gated D Latch
Latch

• Output q gets value from input d only when we is
  high
• we stands for write enable, think of it as a load
  signal

LATCH Symbol
Symbols are abstractions!
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Register
Latch

• A computer register is a place to store a
  collection of bits
• Very fast memory
• Numbered right to left (LSB on the right)

d3
d1
d2
d0
we
d
D-Latch
D-Latch
D-Latch
D-Latch
we
Register
q
REGISTER Symbol
q3
q1
q2
q0
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Memory
Memory

• A collection of addressable locations
• Address selects which location to read from or
  write to

A memory with n address wires has 2n
locations. The number of data wires in equal the
number of data wires out. Memory is changed with
we is asserted. q always reflects the contents
stored at the addressed memory location. Memory
can be viewed as a large collection of slower
registers.
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Building a Memory From Latches
Memory
writeEnable
d input
q0
2-to-4 Decoder
00
we
Register
q1
01
we
Register
q output
q2
10
we
Register
q3
11
we
Register
a1
a0
MEMORY Symbol
This is a functional view. The key parts are
address decoder memory cells (registers)
output selector (mux)
address
n 2
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A 12-Bit Memory
Memory

• 4 words, each 3 bits wide

Word line 00
Word line 01
Only one word line is high at any given time.
Word line 10
Word line 11
Latch
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Reading a 12-Bit Memory
Memory

• Each column forms a sort of multiplexor

Only one of the AND gates in the column will be
enabled. Thus, they allow one row out of 4 to be
selected for reading.
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Writing a 12-Bit Memory
Memory

• 4 words, each 3 bits wide

Write line 00
Write line 01
Write enable signal and write enable AND gates
Write line 10
Write line 11
Depending on state of we signal, zero or one
write lines will be high at any given time.
Latch
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The MSP430
Finite State Machine
You may not know how it works, but you know the
parts its made from!
Status Register
Program Counter
Register
Memory
Multiplexor
Memory Mapped I/O
Bus Driver
16 16-bit Registers
Lots of Gates
Arithmetic Logic Unit
Instruction Register
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Quiz
Quiz

• 1. What is a bi-stable circuit?
• 2. Draw a logic circuit (using N and P type
  transistors) for a 3 input NAND gate.
• 3. With a RS NAND latch, why cant R and S be low
  at the same time?
• 4. How is Q set with the following latch?

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Sequential State Machine
Finite State Machine

• Another type of sequential circuit
• Combines combinational logic with storage
• Remembers state, and changes output (and state)
  based on inputs and current state

State Machine
Inputs
Outputs
Combinational Logic Circuit
Storage Elements
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State of a System
Finite State Machine

• The state of a system is a snapshot of all the
  relevant elements of the system at the moment the
  snapshot is taken.
• Examples
• The state of a basketball game can be represented
  by the scoreboard (ie. number of points, time
  remaining, possession, etc.)
• The state of a tic-tac-toe game can be
  represented by the placement of Xs and Os on
  the board.

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State Diagram
Finite State Machine

• Our lock example has four different states,
  labeled A-D
• A The lock is not open, and no relevant
  operations have been performed.
• B The lock is not open, and the user has
  completed the R-13 operation.
• C The lock is not open, and the user has
  completed R-13, followed by L-22.
• D The lock is open.

Open 0

• State Diagram shows states and actions that cause
  a transition between states.

Open 0
Open 0
Open 1
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Finite State Machine
Finite State Machine

• A description of a system with the following
  components
• A finite number of states
• A finite number of external inputs
• A finite number of external outputs
• An explicit specification of all state
  transitions
• Often described by a state diagram.
• Inputs trigger state transitions.
• Outputs are associated with each state (or with
  each transition).
• Frequently, a clock circuit triggers transition
  from one state to the next.
• At the beginning of each clock cycle, the state
  machine makes a transition, based on the current
  state and the external (or internal) inputs.

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FSM Implementation
Finite State Machine

• Combinational logic
• Determine outputs and next state.
• Storage elements
• Maintains state representation.

State Machine
Inputs
Outputs
Combinational Logic Circuit
Storage Elements
Clock
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Storage Master-Slave Flipflop
Finite State Machine

• A pair of gated D-latches isolates next state
  from current state.

During 1st phase (clock1),previously-computed
statebecomes current state and issent to the
logic circuit.
During 2nd phase (clock0),next state, computed
bylogic circuit, is stored inLatch A.
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Storage Master-Slave Flipflop
Finite State Machine
HOLD
SET/RESET
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Storage Master-Slave Flipflop
Finite State Machine
HOLD
SET/RESET
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Simple FSM Example
Finite State Machine
Combinational Logic
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Simple FSM Example (Lab 2)
Finite State Machine
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Storage Elements
Finite State Machine

• Each master-slave flip flop stores one state bit.
• The number of storage elements (flip flops)
  needed is determined by the number of states (and
  the representation of each state).
• Examples
• Sequential lock
• 4 states 2 bits
• Basketball scoreboard
• 7 bits for each score, 5 bits for minutes, 6 bits
  for seconds, 1 bit for possession arrow, 1 bit
  for half,
• Blinking traffic sign
• 4 states 2 bits

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Finite State Machine Example
Finite State Machine

• A blinking traffic sign
• No lights on
• 1 2 on
• 1, 2, 3, 4 on
• 1, 2, 3, 4, 5 on
• Repeat as long as switchis turned on

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4
1
5
2
DANGERMOVERIGHT
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Traffic Sign State Diagram
Finite State Machine
Transition on each clock cycle.
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Traffic Sign Truth Tables
Finite State Machine
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Traffic Sign Logic
Finite State Machine
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From Logic to Data Path
Finite State Machine

• The data path of a computer uses logic toprocess
  information.
• Combinational Logic
• Decoders -- convert instructions into control
  signals
• Multiplexers -- select inputs and outputs
• ALU (Arithmetic and Logic Unit) -- operations on
  data
• Sequential Logic
• State machine -- coordinate control signals and
  data movement
• Registers and latches -- storage elements

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MSP430 Finite State Machine
Finite State Machine
DECODENOCLKMOVEVSRC EVDSTCLK1MOV,RdD,ROXRd
STORE EVSRCCLK1MOV,RsS,ROXRsEVDST STORECLK1
MOV,RdALU,RWE,RIXRdFETCH ...
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