Andrew Scott

1
Reconfigurable Computing in Undergraduate
Engineering at AAMU

• Andrew Scott
• Department of Electrical Engineering
• Alabama AM University
• andrew.scott_at_aamu.edu
• Sponsored by NSF UNC Charlotte
• May 9, 2008

2
Points of Discussion

• EE at AAMU
• Student Preparation
• Why Reconfigurable Computing?
• Hardware availability
• Educational Objectives
• Results
• Evaluation
• Conclusions

3
EE at AAMU

• Located in Huntsville, AL
• Historically Black College/University (HBCU)
• 5000 undergraduates total
• Engineering Program (CE/ME/EE) about 10 years old
• EE program about 250 students
• 25 graduates/yr
• General (35)
• Microelectronics Option (15)
• Computer Option (50)
• MS program in Fall 2008

4
Student Preparation

• Advanced Digital Systems
• High Performance Computing

Programming
Sophomore
Junior
Freshmen
Senior
5
Why Reconfigurable Computing?

• Augment existing course - EE 425
• High Performance Computing
• Networks
• New Technology
• FPGA
• GPU
• Cell Processors

6
Hardware Availability

• Alabama Supercomputer Authority
• State owned facility
• Free usage for education
• SGI Altix
• DMC
• Cray XD1
• 144 CPUs
• 1 FPGA Chassis
• 6 Xilinx Virtex 4
• LX160

7
Educational Objectives

• Implement as a module into existing High
  Performance Computing course (EE 425, Fall 2007)
• Evaluate student performance and level of success
• If successful,
• Increase exposure in the High Performance
  Computing course
• Possibly offer as a stand-alone Special Topics
  course

8
Implementation

• 4 class periods
• Discussed Available Tools
• VHDL/HDL
• Xilinx ISE
• Impulse C
• Project
• Utilized canned IP blocks
• Studied and implemented CRAY mince (minimal
  compute engine) example.

9
mince functionality

• 1. A Bit Error Rate Test1 that can exercise the
  QDR II RAM interfaces.
• 2. A Bit Error Rate Test (BERT) that can exercise
  the RapidArray Transport interface.
• 3. A bridging function that allows an SMP to
  access the Acceleration FPGAs local QDR II RAM.
• 4. A set of configuration and status registers
  that allow a processing node to configure and
  monitor the device.
• 5. The ability to interrupt the processing node
  to notify it that the BERT test of the RapidArray
  Transport interface is complete.

10
Student Results

• Majority of students overwhelmed
• amount of required detail,
• complexity of processes
• 75 project completion rate
• Despite very specific instructions
• Difficulty grasping system level
• A level of enthusiasm and excitement (25)

11
Evaluation

• Students were ill prepared
• HDL/VHDL
• FPGA hardware familiarity
• Interface FPGA design with C code.
• Some positive results
• Piqued student interest
• Helped with Senior Design Projects

12
Conclusions

• Bolster lower-level supporting classes.
• Continue to offer module in EE 425 course.
• Increase amount of class time on topic.
• Re-evaluate after new class offering.
• Seek innovative teaching tools. (UNCC workshop?)

13
Bolster Student Preparation
Continue offering High Performance Computing
course
Programming
Sophomore
Junior
Freshmen
Added a required lab (standalone FPGA based),
EE320L
Add lab(s) to interface with external FPGA board?
Increase exposure to VHDL/HDL tools (Xilinx?)
Senior
Require EE specific programming courses, EE 101
and EE109
Encourage FPGA related projects
14
QUESTIONS?