SelfResetting Latches for Asynchronous Micropipelines

1
Self-Resetting Latches for Asynchronous
Micropipelines

• Tiberiu Chelcea, Girish Venkataramani, Seth C.
  Goldstein
• Department of Computer Science
• Carnegie Mellon University

2
Introduction

• Micropipelines
• Simple templates used to build asynchronous
  systems
• Many styles, each with unique performance and
  energy characteristics
• Choice of ASU has impact on performance and power
  consumption

3
Existing ASU Implementations
computation
wait for new inputs
computation
inside pipeline

• Incr. power consumption

• Fast

• Low power consumption

• Slow

4
Contribution Self-Resetting Latches

• Combine
• Performance of latch-based ASUs
• Low-energy consumption of ETDFF-based ASUs
• Results
• Energy-delay
• 41 better than latch implementations
• 15 better than ETDFF implementations
• Performance
• 13 slower than latch implementations
• 14 faster than ETDFF implementations

5
Self-Resetting Latches Key Ideas

• For speed use latches as storage elements, but
• Add more control on opening and closing
• Latches normally close to eliminate glitches
• Open them when data is stable but
• Before starting a handshake with the consumer

6
Self-Resetting Latches Implementation
trigger
Dout
Din
ASU
Done
7
SR Latch Controller
STG specification

• Eliminate glitches
• open only after data is ready
• close as soon as data latched
• Eliminate overheads
• open before handshake starts

8
SR Latches in Micropipeline Stages
Ack
out
CU
HS
cntrl
FU
Req
in
Data
Delay
out
ASU
Data
FU
in
Req
circuit
out
Ack
in

• Substitute any ASU with SR-based ASU
• Tap data ready signal to the Enable input of ASU

9
Results Experimental Setup

• Study of SR latch behavior
• Speed characterization
• Study of SR latches in a large system
• Integrated SR latches into CASH (C -gt layout
  compiler)
• Compiled several Mediabench kernels using
• SR latch ASUs
• Latch-based ASUs
• ETDFF ASUs
• Characterize their speed and energy efficiency
• Results
• 180nm ST Micro technology library
• Post-layout

10
Latency 1-bit ASU
11
Speed Mediabench Kernels
shorter faster
12
Energy-Delay Mediabench Kernels
shorter better energy-delay
13
Conclusions

• Introduced SR-latches, novel asynchronous storage
  unit
• Provides good performance, while
• Preserving low-power consumption
• Key idea
• Manipulate the timing of opening closing for
  latches