Asynchronous Communication Mechanisms Using Self-timed Circuits

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Asynchronous Communication Mechanisms Using
Self-timed Circuits

• Fei Xia, Alex Yakovlev, Delong Shang,
• Alex Bystrov, Albert Koelmans,
• David Kinniment
• Asynchronous Systems Laboratory
• University of Newcastle upon Tyne
• Async2000,Eilat-Israel, C

2
Objectives

• To study a class of async comms previously used
  in (software) systems for embedded applications
  for potential use in SOCs

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Objectives

• To study a class of async comms previously used
  in (software) systems for embedded applications
  for potential use in SOCs
• Salient features of this class
• Bulk data transfer (medium,possibly varying, size
  frames)
• Between independent motive powers (clock
  domains), hence need to eliminate mutual blocking
• Issues of coherence and freshness of data

4
Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

5
Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

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Asynchronous Communication
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Asynchronous Communication
Rita (Reader)
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
Is it really Asynchronous Communication?
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
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Asynchronous Communication
Is it really Asynchronous Communication?
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Asynchronous Communication
Bounded buffer is still Synchronous Communication!
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Asynchronous Communication
Solution ?
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Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

38
Mechanisms for Async Comm
Solution1 Writer bins the new item when buffer
is full
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Mechanisms for Async Comm
Solution1 Writer bins the new item when buffer
is full
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Mechanisms for Async Comm
Solution1 Reader re-reads the old item when
buffer is empty
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Mechanisms for Async Comm
Solution1 Reader re-reads the old item when
buffer is empty
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Mechs for Async Comm
Solution1 implemented as a non-blocking FIFO
(IEEE TC VLSI Newsletter Fall 1998)
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Mechs for Async Comm
Solution2 Writer overwrites the item when buffer
is full
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Mechs for Async Comm
Solution2 Writer overwrites the item when buffer
is full
But this involves locking the whole buffer!
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Mechs for Async Comm
Is a (non-blocking) FIFO buffer a proper solution
for the News type of data?
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Mechs for Async Comm
No! News maybe out of date when it reaches Reader
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Mechs for Async Comm

• Required Properties
• Total Asynchrony Reader and Writer, independent
  motive powers cannot wait
• Coherence no data corruption, thus items cannot
  be written/read in part
• Freshness Reader must read the item written
  most recently by Writer

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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence
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Data Coherence Violation
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Data Freshness
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Data Freshness
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Data Freshness
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Data Freshness
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Data Freshness
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Data Freshness
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Data Freshness Violation
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Async Comm Mechanisms
How to maintain Asynchrony, Coherence and
Freshness?
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Async Comm Mechanisms
How to maintain Asynchrony, Coherence and
Freshness?
Control variables
ACM
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Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

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Slot Mechanisms

• How many slots is enough?

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Slot Mechanisms

• How many slots is enough?
• One cannot be both async and coherent

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Slot Mechanisms

• How many slots is enough?
• One cannot be both async and coherent
• Two can be made async and coherent
• but no freshness

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Slot Mechanisms

• Three or Four Slots are sufficient to achieve
  freshness
• We used algorithms due to Hugo Simpson (BAe)

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Three-slot ACM
Writer
Reader
s1
23.12
s2
27.12
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
27.12
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
27.12
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
27.12
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
27.12
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
03.01
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
03.01
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
03.01
s3
30.12
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Three-slot ACM
Writer
Reader
s1
02.01
s2
02.01
03.01
s3
05.01
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Three-slot ACM
Writer
Reader
s1
02.01
s2
03.01
s3
05.01
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Three-slot ACM
Writer
Reader
s1
02.01
s2
03.01
s3
05.01
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Three-slot algorithm
Reader
Writer
wr dninput w0 ln w1 ndiffer(l,r)
r0 rl rd outputdr
n (new), l(last), r(read) 3-valued vars
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Three-slot algorithm
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Four-slot ACM
Writer
Reader
s0
s1
v0
v1


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Four-slot algorithm
Reader
Writer
wr dn,sninput w0 sn sn w1 ln
nr
r0 rl r1 vs rd outputdr,vr
n (new), l(last), r(read) binary vars
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Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

87
Implementation of ACM
Data In
Data Out
writer
reader
start
done
start
done
steering
ACM control part
wr-req
Write control
Statement logic (mutex, latches, selectors)
Read control
r0-req
wr-ack
r0-ack
w0-req
rd-req
w0-ack
rd-ack
w1-req
w1-ack
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Implementation of ACM
Data In
Data Out
writer
reader
start
done
start
done
n,r,l
steering
wr-req
Write control
Read control
Statement logic (mutexes, latches, selectors)
r0-req
wr-ack
r0-ack
w0-req
rd-req
w0-ack
rd-ack
w1-req
w1-ack
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Write Control STG
start
done-
start-
done
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Write Control logic direct translation from STG
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3-slot ACM design
Rw0
Rr0
write control
mutex
read control
Gw0
Gr0
w0-req/ack
w1-req/ack
r0-req/ack
l
differ reg n
reg l
reg r
r
n
l
r
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3-slot ACM design
Rw0
Rr0
write control
mutex
read control
Gw0
Gr0
w0-req/ack
w1-req/ack
r0-req/ack
l
differ reg n
reg l
reg r
r
n
l
r
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Differ and register logic
differ
register
l1
l2
n1
l3
w1-ack
n2
r1
r2
n3
r3
w1-req
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3-slot ACM design
Rw0
Rr0
write control
mutex
read control
Gw0
Gr0
w0-req/ack
w1-req/ack
r0-req/ack
l
differ reg n
reg l
reg r
r
n
l
r
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Write control circuit STG
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Write control ckt from Petrify
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Analogue simulation
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3-slot vs 4-slot performance
Time for control statements
statements 3-slot min time ns 4-slot min time ns
w0w1 4.19 9.39
r0(r1) 1.38 3.47
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Other analyses of ACM designs

• Response time analysis for Write and Read using
  stochastic Petri nets (tool PET by Xie and
  Beerel)
• The circuit response varies with the relative
  frequency of Write/Read, e.g. higher Write
  frequency increases the chance for Read to hit
  arbitration and hence be delayed.

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Response time analysis
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Other analyses of ACM designs

• Digital simulation using Verilog models for
  Writer, Reader and ACM
• The circuit is a coherent, fresh and
  non-blocking mechanism. Clear indication of data
  over-writing (skipping) and re-reading (olding)

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Digital simulation
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Digital simulation
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Digital simulation
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Digital simulation
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Digital simulation
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Digital simulation
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Other analyses of ACM designs

• Stochastic analysis of skipping and olding using
  Generlised SPN (GSPN) tool

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Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

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Comparison with FM solutions

• Fundamental Mode designs for 4-slot were proposed
  by H. Simpson and E. Campbell
• Writer and Reader time (with individual motive
  powers) their wr, w0, w1 and r0, r1, rd
  operations, allowing enough time for potential
  m/stability to settle on control variables n, r, l

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Comparison with FM solutions

• Self-timed (I/O mode) design
• can potentially run faster than the FM design
• makes it possible to operate in FM with
  practically bounded Read and Write control
  actions
• Theoretical possibility of unbounded
  metastability gt trade-off between temporal
  independence and data coherence

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Outline

• Asynchronous Communication
• Mechanisms for Async Communication
• Three and Four Slot ACMs
• Speed-independent implementation
• Comparison with FM solutions
• Conclusions

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Conclusions

• Speed-independent VLSI (AMS 0.6mm CMOS)
  implementation of 3- and 4-slot ACMs for News
  (reference) data transfers
• Minimum granularity of blocking a binary
  variable
• Practical boundedness of Slot Acquisition Time
• For non-handshake interfaces dones can be
  dropped
• What is the right size of data blocks for such
  ACMs?

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VLSI design layout
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VLSI Design layout
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And now
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Hag Sameah!
Everybody to the
C