SingleEventUpset Awareness in FPGA Routing

1
Single-Event-Upset Awareness in FPGA Routing

• Shahin Golshan and Eli Bozorgzadeh
• Center for Embedded Computing Systems (CECS)
• Computer Science Department
• University of California, Irvine

2
Introduction

• Tolerance to single event upsets (SEU) is a key
  challenge in nanoscale SRAM-based FPGAs
• Smaller feature size and higher density
• Lower operating voltage
• Majority of SRAMs are configuration SRAMs
• SEU in configuration bits causes soft error
• Bit flip in configuration SRAM
• Only a subset of configuration bits affect the
  design due to SEU
• Referred as CARE BITS
• More care bits leads to more susceptibility to
  SEU
• More frequent reconfiguration (scrubbing)

3
Care Bits

• Care bit
• If flips, an error is injected in design
• The majority of the care bits correspond to the
  routing architecture
• Around 90 (as reported by Reddy, et. al. in
  VLSI05)
• Our contribution
• Analysis of care bits in routing architecture
• Design a SEU-aware router to minimize routing
  care bits

Error!
4
Related Work

• SEU analytical modeling and estimation
• G. Asadi et. al. (FPGA05)
• Architectural features for SEU mitigation
• S. Srinivasan, et. al. (ICCAD04)- asynchronous
  SRAM-based FPGAs
• Designs for SEU detection and correction
• S. Reddy et. al. (VLSI05)- bridging fault
  detection
• B. Pratt et. al. (MAPLD05)- partial TMR on
  persistent bits
• Soft error mitigation in place and route tools
• H. Zarandi, et. al.(ISQED06)- focus on bridging
  faults
• L. Sterpone et. al. (TC06)- TMR based designs

5
Routing Graph

• Routing graph an abstract of the routing
  architecture

• General FPGA switch module and connection module
• The routing graph extracted from (a)

6
Types of Care bits

• 1-per-net care bits
• The closed switches between the segments of a net
  (open fault)

• 0-per-net care bits
• Any open switch that hurts the functionality of
  one net when it gets closed (short fault)

NET A
NET B
NET A
DANGLING
ERROR!

• Cross-net care bits
• Any interference on nets caused by closing an
  open switch between two different nets (bridging
  fault)

7
SEU-Aware FPGA router

• The problem of SEU-aware routing can be stated
  as
• Given a routing graph and a set of
  multi-terminal nets, route each net with least
  care cost, where care cost is the number of
  routing care bits

• Challenges
• Finding minimum care cost route
• care cost of a path is an additive function of
  the care costs of its nodes ? include care cost
  in min cost routing algorithms to find the
  optimum path
• Impact on critical path delay and routability
• Reducing 1-per-net care bits inherently reduces
  delay
• Reducing cross-net care bits leads to less
  adjacent nets
• Can hurt routability and delay

• Our cost function for routabilty, delay and care
  cost associated with node v is

8
Care Cost Computation
9
Care Cost Computation While Routing
10
Care Cost Computation While Routing
11
Care Cost Computation While Routing
12
Care Cost Computation While Routing
13
Care Cost Computation While Routing
14
Experiment Setup

• Implemented SEU-aware router on top of
  timing-driven VPR router
• FPGA Architecture
• Virtex-like routing segmentation
• Two 4-input LUTs per CLB
• Buffered switches (mux-based inputs and
  demux-based outputs) in connection modules
• Experiments
• On MCNC Benchmark
• Evaluated care bits and critical path delay
• Compared with timing-driven VPR

15
Experiment Results-1

• The switches used in the switch modules are
  tri-state buffers
• Compared to VPR, the delay degradation is only
  1.45

• Significant reduction in adjacency between the
  nets leads to decrease in number of bridging
  faults and improves testability

16
Experiment Results-2

• By using 50 pass-transistors and 50 buffered
  switches, we can both reduce the 0-per-net care
  bits and cross-net care bits without contention

• Reducing the total number of care bits makes the
  design less susceptible toward SEU errors

17
Experiment Results-3

• All the configuration bits of used MUXes are care
  bits
• In asymmetrical SRAMs (ASRAM), the susceptibility
  of a ASRAM depends on the value it is holding S.
  Srinivasan, et. al.
• In ASRAM-0, 0?1 upsets are less probable than 1?0
  upsets
• We favor 0s in MUX encoding over 1s

18
Conclusion and Future Work

• We proposed care bit reduction during FPGA
  routing
• SEU-aware router reduces the care bits with
  negligible delay degradation
• The bridging fault rate has improved by
  drastically reducing the cross-net care bits
• Using ASRAM-0 FPGA, SEU-aware router can improve
  the FIT rate by 35
• Ongoing Work
• Including power-awareness in SEU-aware router

19

• THANKS