Digital Integrated Circuits A Design Perspective

1
Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
The Devices
July 30, 2002
2
Goal of this chapter

• Present intuitive understanding of device
  operation
• Introduction of basic device equations
• Introduction of models for manual analysis
• Introduction of models for SPICE simulation
• Analysis of secondary and deep-sub-micron effects
• Future trends

3
The Diode
Mostly occurring as parasitic element in Digital
ICs
4
Depletion Region
5
Diode Current
6
Forward Bias
Typically avoided in Digital ICs
7
Reverse Bias
The Dominant Operation Mode
8
Models for Manual Analysis
9
Junction Capacitance
10
Diffusion Capacitance
11
Secondary Effects
0.1
)
A
(
0

D
I
0.1
25.0
15.0
5.0
5.0
0
V
(V)
D
Avalanche Breakdown
12
Diode Model
13
SPICE Parameters
14
What is a Transistor?
15
The MOS Transistor
Polysilicon
Aluminum
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MOS Transistors -Types and Symbols
D
D
G
G
S
S
Depletion
NMOS
Enhancement
NMOS
D
D
G
G
B
S
S
NMOS with
PMOS
Enhancement
Bulk Contact
17
Threshold Voltage Concept
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The Threshold Voltage
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The Body Effect
20
Current-Voltage RelationsA good ol transistor
21
Transistor in Linear
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Transistor in Saturation
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Current-Voltage RelationsLong-Channel Device
24
A model for manual analysis
25
Current-Voltage RelationsThe Deep-Submicron Era
26
Velocity Saturation
Constant velocity
Constant mobility (slope µ)
27
Perspective
I
D
Long-channel device
V
V
GS
DD
Short-channel device
V
V
V
- V
DSAT
DS
GS
T
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ID versus VGS
linear
quadratic
quadratic
Long Channel
Short Channel
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ID versus VDS
Long Channel
Short Channel
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A unified modelfor manual analysis
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Simple Model versus SPICE
(A)
D
I
V
(V)
DS
32
A PMOS Transistor
VGS -1.0V
VGS -1.5V
VGS -2.0V
Assume all variables negative!
VGS -2.5V
33
Transistor Model for Manual Analysis
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The Transistor as a Switch
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The Transistor as a Switch
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The Transistor as a Switch
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MOS CapacitancesDynamic Behavior
38
Dynamic Behavior of MOS Transistor
39
The Gate Capacitance
40
Gate Capacitance
Cut-off
Resistive
Saturation
Most important regions in digital design
saturation and cut-off
41
Gate Capacitance
Capacitance as a function of VGS (with VDS 0)
Capacitance as a function of the degree of
saturation
42
Measuring the Gate Cap
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Diffusion Capacitance
Channel-stop implant
N
1
A
Side wall
Source
W
N
D
Bottom
x
Side wall
j
Channel
L
Substrate
N
S
A
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Junction Capacitance
45
Linearizing the Junction Capacitance
Replace non-linear capacitance by large-signal
equivalent linear capacitance which displaces
equal charge over voltage swing of interest
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Capacitances in 0.25 mm CMOS process
47
The Sub-Micron MOS Transistor

• Threshold Variations
• Subthreshold Conduction
• Parasitic Resistances

48
Threshold Variations
Low
V

threshold
Long-channel threshold
DS
VDS
L
Threshold as a function of
Drain-induced barrier lowering
the length (for low
V
)
(for low
L
)
DS
49
Sub-Threshold Conduction
The Slope Factor
S is DVGS for ID2/ID1 10
Typical values for S 60 .. 100 mV/decade
50
Sub-Threshold ID vs VGS
VDS from 0 to 0.5V
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Sub-Threshold ID vs VDS
VGS from 0 to 0.3V
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Summary of MOSFET Operating Regions

• Strong Inversion VGS gt VT
• Linear (Resistive) VDS lt VDSAT
• Saturated (Constant Current) VDS ? VDSAT
• Weak Inversion (Sub-Threshold) VGS ? VT
• Exponential in VGS with linear VDS dependence

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Parasitic Resistances
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Latch-up
55
Future Perspectives
25 nm FINFET MOS transistor