Digital Integrated Circuits A Design Perspective

1
Digital Integrated CircuitsA Design Perspective
Jan M. Rabaey Anantha Chandrakasan Borivoje
Nikolic
ManufacturingProcess
July 30, 2002
2
CMOS Process
3
A Modern CMOS Process
Dual-Well Trench-Isolated CMOS Process
4
Circuit Under Design
5
Its Layout View
6
The Manufacturing Process
For a great simplified tour through an IC
foundary, check http//www.necel.com/v_factory/en/
index.html
7
Photo-Lithographic Process
optical
mask
oxidation
photoresist coating
photoresist
removal (ashing)
stepper exposure
Typical operations in a single
photolithographic cycle (from Fullman).
photoresist
development
acid etch
process
spin, rinse, dry
step
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Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
(b) After oxidation and deposition
SiO
of negative photoresist
2
Si-substrate
UV-light
Patterned
(e) After etching
optical mask
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
9
CMOS Process at a Glance
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CMOS Process Walk-Through
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CMOS Process Walk-Through
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CMOS Process Walk-Through
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CMOS Process Walk-Through
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Metallization
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Design Rules
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3D Perspective
Polysilicon
Aluminum
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Design Rules

• Interface between designer and process engineer
• Guidelines for constructing process masks
• Unit dimension Minimum line width
• scalable design rules lambda parameter
• absolute dimensions (micron rules)

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CMOS Process Layers
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Layers in 0.25 mm CMOS process
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Intra-Layer Design Rules
4
Metal2
3
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Transistor Layout
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Vias and Contacts
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Select Layer
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CMOS Inverter Layout
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Layout Editor
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Design Rule Checker
poly_not_fet to all_diff minimum spacing 0.14
um.
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Sticks Diagram

• Dimensionless layout entities
• Only topology is important
• Final layout generated by compaction program

28
Packaging
Interface between silicon and the outside world
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Packaging Requirements

• Electrical Low parasitics
• Mechanical Reliable and robust
• Thermal Efficient heat removal
• Economical Cheap

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Bonding Techniques
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Tape-Automated Bonding (TAB)
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Flip-Chip Bonding
33
Package-to-Board Interconnect
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Package Types
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Package Parameters
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Multi-Chip Modules