Counter T flipflops

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Counter (T flip-flops)
Up-Counter 0000 0001 0010 0011 0100 0101 0110 0111
1000 1001 1010 1011 1100 1101 1110 1111 0000
T
K
J
CLR
Q
Q
T0 Hold T1 Change Asynchronous Clear
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Bit 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1
1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0
0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0
0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0
Bit 2 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1
1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1
0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0
0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0
LSB -Bit 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0
0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1
0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1
MSB -Bit 3 0 0 0 0 0 0 0 1 0 0 1 0 0
0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1
1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1
1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0 0 0 0
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A 4-bit up-counter
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Read-Only Memory (ROM)
2n in K
Read-only memory is nonvolatile
x W ROM
n address lines
Data
For example, a ROM with 8 data lines and 12
address lines is a 4K x 8 ROM. (1K 2 10 1024)
W
W data lines
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Types of ROM
ROM Read-only memory. Permanently programmed
by the die at the silicon foundry. Manufactured
in the thousands. PROM Programmable read-only
memory. Write-once memory. EPROM Erasable
Programmable read-only memory. Write with a
computer interface. Erase with ultraviolet
light. EEPROM Electrically Erasable
Programmable read-only memory. Write with a
computer interface. Erase with a special
higher-voltage mode.
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Read-Write Memory (RAM)
W input data lines
W
RAM memory is volatile
2n in K
x W RAM
n address lines
Read
Write
Data
Enable
W
For example, a RAM with 16 data lines and 20
address lines is a 1M x 16 RAM. (2 20 2
10 x 2 10 1K x 1K 1M)
W output data lines
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Structure of Memory
2n in K
x W ROM
Memory 0
n address lines
Memory 1
Data
W
Memory 2n-1
W data lines
2n x 1 Mux
2n x 1 Mux
2n x 1 Mux
...
D0
D1
DW-1
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Homework for Tuesday, September 4 (part 2)
1) Draw the circuit for a 4-bit down-counter
using T flip-flops 2) Modify the 4-bit
up-counter shown in class today to convert it to
a decade counter. That is, the count should go
0000?0001?... ?1001 ?0000. Hint Construct a
logic circuit to control the asynchronous clear
inputs. Be careful to note that the clear
operation occurs immediately when the CLR line is
pulled low and is not controlled by the clock.
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Expanding Inputs

• Use n address lines to address 2n locations
• The less significant address lines are run in
  parallel to all the chips to select locations
  within the chip
• The more significant address lines are used as
  select line inputs into a decoder. The decoder
  outputs are used to control the enable lines of
  the chips.

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For example, four 4 x 1 Mux are needed to create
a 16 x 1 Mux

• For a 16 x 1 Multiplexer
• 4 address lines are needed (24 16)
• 2 address lines are needed for each 4 x 1 MuX (22
  4). Address lines A1and A0 are run to the
  select inputs of each 4x1 MuX
• 2 address lines, A3 and A2, provide the select
  line inputs to a 2-into-4 decoder
• The 4 outputs of the decoder control the enable
  lines of the four 4x1 MuX

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Outputs

• Where the outputs of the multiple chips are
  always such that only one output is active while
  the other outputs are identically 0, then the
  outputs may be collected in an m-input OR gate
• If an enable input is desired for the larger
  circuit which has been created, then m
  multiplexers are needed to create m data lines
• The more significant address lines are used as
  select line inputs into the multiplexers
• For this example, a 16x1 MuX has one output

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Tri-State Gates

• In a large system, the address lines would have
  to drive a very large number of
  inputs--exceeding the fan-out capacity of the
  chip controlling the address line
• The solution is using tri-state gates gates
  with 3 states a 1 state, a 0 state, and a
  high impedance state
• High impedances look like open circuits

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Tri-State Buffer
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Homework for Tuesday, September 4(part 3)
1) Mano problem 2-1 2) Mano problem 2-3 3)
Mano problem 2-15 4) Mano problem 2-19 5) Mano
problem 2-22