Questions on VerilogA

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Questions on Verilog-A

• What is the speed difference?
• What is the memory use difference?
• What is the model implementation lead time
  difference? (Note not model development time,
  but time to implement a model in a simulator)
• How can model implementation consistency be
  verified?
• How can Verilog-A implementation consistency be
  verified?
• Can Verilog-A do NQS? (specifically for the
  HiSIM2 NQS model)
• Can Verilog-A do excess phase?
• What forms of debuggers are available for
  Verilog-A?
• Can human-readable C code be generated from
  Verilog-A? If so, what can the CMC do to ensure
  that this is available?
• Should the CMC provide/control a Verilog-A
  compiler? If so, how should this be done?
• What model development teams are able to produce
  C code?
• How can the CMC ensure correctness of derivatives
  and matrix stamp for manually-generated C code?
• What features for RF or "fast-SPICE" simulators
  are difficult to implement based on Spice3 C code
  only?

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1. What is the speed difference?

• Need test suite
• Mica we have seen that the speed difference can
  be small
• VBIC with self-heating
• C-code from ADMS was 10 faster than hand-coded
  implementation

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2. What is the memory use difference?

• Need test suite
• Mica memory footprint difference should be zero

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3. What is the model implementation lead time
difference?
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4. How can model implementation consistency be
verified?

• This is really independent of Verilog-A
• Need test suite
• CMC QA subcommittee
• a model should come with extensive test
  specifications and reference test results
• documented process, test specification format,
  example code for automated testing are being
  generated

6
5. How can Verilog-A implementation consistency
be verified?

• Need test suite
• CMC is looking into option of funding a Verilog-A
  test suite with funds available in 2005

7
6. Can Verilog-A do NQS?

• Need test suite
• For models of form
• introduce extra node for qnqs
• calculate Qqs from terminal voltages
• set up balance equation for qnqs
• simulator solves for qnqs
• NQS part is simple, but the model then needs to
  re-calculate the rest of the state of the device
  self-consistently width qnqs

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7. Can Verilog-A do excess phase?

• Need test suite
• Has been in VBIC for many years

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8. What forms of debuggers are available for
Verilog-A?
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9. Can human-readable C code be generated from
Verilog-A? If so, what can the CMC do to ensure
that this is available?
11
10. Should the CMC provide/control a Verilog-A
compiler? If so, how should this be done?
12
11. What model development teams are able to
produce C code?
13
12. How can the CMC ensure correctness of
derivatives and matrix stamp for
manually-generated C code?
14
13. What features for RF or "fast-SPICE"
simulators are difficult to implement based on
Spice3 C code only?
15
Executable Specification vs.Final Implementation

• Verilog-A
• simplifies model development
• enables easy dissemination of code for test
• simplifies having multiple people implement
  enhancements
• Options
• CMC requires Spice3f5 code from developers
• CMC requires Verilog-A code from developers and
  is responsible for C code
• CMC requires Spice3f5 code from developers and
  simulator implementers are responsible for C code