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Communicating Transaction Processes

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Title: Communicating Transaction Processes


1
Communicating Transaction Processes
  • P.S. Thiagarajan
  • National University of Singapore
  • Joint Work with
  • Abhik Roychoudhury

2
The Main Features
  • To support System Level Design
  • One Level of Abstraction higher than C, C, VHDL
    ..
  • UML-compatible
  • MSCS Asynchronous control flow
  • Based on MSCs (Message Sequence Charts)
  • Sequence Diagrams

3
Why System Level Design?
  • Closer to end-use(r) .
  • Less detailed and more architecture-neutral.
  • Easier reuse/adaptaton.
  • Easier to verify.
  • Safety-critical applications need to be correct.
  • Catch design errors early.
  • Coupling with a correct-by-construction synthesis
    method is an attractive option.

4
What is Available?
  • Data flow graphs.
  • Automata of various kinds.
  • Petri nets.
  • State charts.
  • Esterel, Lustre.
  • SDL, UML.

5
Why UML-compatible?
  • UML is getting rapidly established as a standard.
  • Mainly in software engineering projects
  • Increasingly so in embedded systems domain.
  • Offers a suite of graphical notations
  • Multiple views
  • Behavioral and structural diagrams.
  • Object orientation.
  • Reuse, adaptation

6
An Idealized Design Flow
Requirements
High Level Description
Exec. Specifications.
Intermediate representation
SW/HW Implementation.
7
Requirements and Exec. Specifications
  • Requirements Message Sequence Charts (MSCs)
  • Exec. Specifications
  • State charts.
  • UML supports both but no clear distinction made.
  • Other Exec. Spec.
  • Petri nets,
  • MPAs (Message Passing Automata), .

8
MSCs
  • Message Sequence Charts
  • Describe scenarios.
  • A finite pattern of interaction between agents
    (object instances,..).
  • A story

9
Message Sequence Charts
U1
R
U2
rq
rq
y
n
10
Message Sequence Charts
U1
R
U2
rq
rq
y
n
11
Message Sequence Charts
U1
R
U2
rq
rq
y
internal action
n
12
Message Sequence Charts
U1
R
U2
rq
rq
internal actions
y
n
13
Message Sequence Charts
U1
R
U2
rq
rq
y
n
14
Message Sequence Charts
U1
R
U2
rq
rq
y
n
15
Message Sequence Charts
U1
R
U2
rq
rq
y
n
16
Message Sequence Charts
U1
R
U2
rq
rq
y
n
17
Message Sequence Charts
U1
R
U2
rq
rq
y
n
18
Message Sequence Charts
U1
R
U2
rq
rq
y
n
19
Message Sequence Charts
U1
R
U2
rq
rq
y
n
20
Message Sequence Charts
U1
R
U2
rq
rq
y
n
21
Message Sequence Charts
U1
R
U2
rq
rq
y
n
22
CTPs
  • Communicating Transaction Processes.
  • An executable spec. mechanism.
  • Based on MSCs.
  • A network of interacting agents.
  • Agents interaction pattern behavior
  • Standard distributed system model
  • Interaction
  • Guarded choice of MSCs.
  • Transaction schemes.

23
Distributed System Models
  • Petri nets
  • Data flow graphs
  • Statecharts
  • Distributed transition systems (many kinds!)
  • Process algebras (CCS, CSP, )

24
I2
I1
PI2
PI1
IB1
IB2
B
P2
25
I2
I1
PI2
PI1
IB1
IB2
B
P2
26
I2
I1
PI2
PI1
IB1
IB2
B
P2
27
I2
I1
PI2
PI1
IB1
IB2
B
P2
28
I2
I1
PI2
PI1
IB1
IB2
B
P2
29
I2
I1
PI2
PI1
IB1
IB2
B
P2
But the boxes will have internal structure. A
complex Transaction Scheme.
30
Transaction Scheme
I2
B
I2
B
I2
B
?2data.present B.free?
?2data.present ?B.free?
? ? 2data.present ?
req
req
y
n
add
data
waitcount2 waitcount2 1
31
?2data.present B.free?
req
y
add
data
32
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
33
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
34
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
35
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
36
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
37
I2
I1
?2data.present B.free?
req
PI2
y
?
PI1
IB1
IB2
add
data
B
38
P11 Transaction Scheme
I1
?1data.present?
??1data.present?
??1data.present?
no-op
data
no-data
?1data.present?
?1data.present?
??1data.present?
39
Analysis Issues
  • Determine whether a CTP is bounded.
  • Determine if a CTP can deadlock.
  • Determine if a CTP is well-formed.

40
Current Status
Case Studies
Modeling
The CTP Model
Verification
Analysis
SMV
ES Representation
Simulation Synthesis
Verilog
41
Current Status
Pankaj Jain Nikhil Jain Kamrul Hasan
Talukdar Tran Tuan Anh Ge Zhiguo
Case Studies
Modeling
The CTP Model
Verification
Analysis
SMV
ES Representation
Simulation Synthesis
Verilog
42
Future Work
  • Add multiple instances of a process.
  • Object features
  • Add timing constraints.
  • Develop the computational model.
  • Interactions with environment (sense, actuate)
  • Computational steps (control law)
  • Schedulability is a key issue.
  • HW/SW Partitioning Architectural mapping
    Synthesis?
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