Q: What is the definition of an engineer

1

• Q What is the definition of an engineer?
• A Someone who solves a problem you didn't know
  you had in a way you don't understand.
• Q When does a person decide to become an
  engineer?
• A When he realizes he doesn't have the charisma
  to be an undertaker.

2
CSE 502NFundamentals of Computer Science

• Fall 2004
• Lecture 22
• Introduction to VHDL

3
Computer-Aided Design

• CAD tools are essential to the design of complex
  parts.
• Logic design
• schematic capture - interactive creation of logic
  diagrams
• hardware description languages - textual
  representation of circuit function
• Design verification
• logic simulation to check circuit behavior
  experimentally
• formal verification tools - automated correctness
  proofs and assertion checking
• timing analysis and simulation
• Implementation
• logic synthesis - convert high level spec. to low
  level gates
• circuit layout - placement of components, routing
  of wires
• details - clock distribution, power, pads, testing

4
Hardware Description Languages

• HDLs allow designers to work at a higher level of
  abstraction than logic gates.
• As with programming languages, HDL descriptions
  are compiled into a lower level representation.
• low level form can be simulated for logical
  correctness
• and, can be converted to a circuit specification
  using a library of primitive components and
  timing/area constraints
• But dont confuse hardware design with software.
• HDL descriptions must reduce to physical hardware
  that can be fit in the physical space available
  and meets timing specs.
• hardware designs are inherently parallel with
  many things going on at once
• on the other hand, software can be used to
  implement much more complex functions than
  hardware alone.
• VHDL (VHSIC Hardware Description Language)
• VHSIC (Very High Speed Integrated Circuit)

5
VHDL Specification of Half Adder
library provides commonly used types and functions
Port declaration defines inputs and outputs.
STD_LOGIC type used for signals.
May have different implementations for a given
module.
CAD software simulates circuit operation.
Signal assignments occur simultaneously.
xor, and are built-in operators
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VHDL Specification of Full Adder

• library IEEE
• use IEEE.STD_LOGIC_1164.ALL
• use IEEE.STD_LOGIC_ARITH.ALL
• use IEEE.STD_LOGIC_UNSIGNED.ALL
• entity fullAdd is
• Port (
• a, b, Ci in std_logic
• S, Co out std_logic )
• end fullAdd
• architecture a1 of fullAdd is
• begin
• S
• Co
• end a1

Compact port declarations
Complex logic expressions.
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What Does VHDL Spec Mean?

• VHDL specifies a circuit, not sequential
  execution. So,
• architecture arch of fulladd is begin
• s
• Co
• end arch
• means

• So, what does this mean?
• architecture foo of bar is begin
• a
• end bar

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Signal Assignments for Vectors

• Example
• entity foo is
• port(a in std_logic
• b in std_logic_vector(2 downto 0)
• c out std_logic_vector(3 downto 0))
• end foo
• architecture bar of foo is begin
• c
• end bar
• defines circuit

9
Conditional Signal Assignment

• Example
• c
• "1101" when a '1' else
• "0100"
• means

• general form
• x
• v1 when f1(a1,b1,...) else
• v2 when f2(a2,b2,...) else
• v3 when f3(a3,b3,...) else
• ... else vN

• x
• (f1(a1,b1,...) and v1) or
• (not f1(a1,b1,...) and
• f2(a2,b2,...) and v2) or
• (not f1(a1,b1,...) and
• not f2(a2,b2,...) and
• f3(a3,b3,...) and v3) or
• ...

?
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Selected Signal Assignment

• Example
• with x select
• c when 11",
• 0100" when others
• means

• Resulting circuit is more compact and faster than
  circuit produced by conditional assignment.

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Important Characteristics of VHDL

• VHDL developed for circuit modelling
  simulation.
• allows specification of hardware behavior
  independent of implementation
• synthesis tools developed later
• not all VHDL specifications can be synthesized
• Signals correspond to wires in circuit.
• language also supports variables - useful in
  behavioral models, testbenches
• best to avoid variables in synthesizable models
  (except loop variables)
• Signal assignments define logic circuits.
• signals on left side of assignment change as
  signals on right side change (exceptions to be
  discussed later)
• not like sequential program execution
• Strong typing in VHDL.
• signal types in expressions must match exactly
• no automatic type conversions
• bit and integer are only built-in types
• extensive support for user-defined types, such as
  std_logic
• std_logic defines 9 values, including 0, 1 and
  undefined

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Processes and if-then-else

• Example
• entity foo is port(
• a, b in std_logic
• c, d out std_logic_vector(3 downto 0))
• end foo
• architecture foo of bar is begin
• process (a, b) begin
• if a / b then
• c
• elsif a '1' then
• c
• else
• c
• end if
• end process
• end foo

process block enables use of complex statement
types
sensitivity list must include all input signals
to process
note that c,d defined under all possible input
conditions - REQUIRED
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Avoiding Unintended Storage

• If value of a signal is not specified for some
  condition, it means that signal is unchanged.
• Example
• process(a,b) begin
• if a '1' then
• x
• elsif b '1' then
• x
• end if -- x retains value when ab0
• end process
• Storage elements are required to implement
  circuit with the specified behavior.
• if one accidentally omits a condition for a
  signal, unintended storage elements are
  synthesized.
• Easy way to avoid unintended storage is to start
  process with assignment of default values to all
  signals assigned a value inside the process.

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Default Values

• Example
• entity foo is port(
• a, b in std_logic
• c, d out std_logic_vector(3 downto 0))
• end foo
• architecture foo of bar is begin
• process (a, b) begin
• c
• if a / b then
• c
• elsif a '1' then
• c
• end if
• end process
• end foo

initial assignments define default values for c
and d
What values are assigned to c, d if we rearrange
so if-then-else comes first?
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For-loops

• entity adder8 is
• Port ( Cin in std_logic
• A, B in std_logic_vector(7 downto
  0)
• S out std_logic_vector(7 downto 0)
• Cout out std_logic)
• end adder8
• architecture arch1 of adder8 is
• signal C std_logic_vector(8 downto 0)
• begin
• process(A,B,C,Cin) begin
• C(0)
• for i in 0 to 7 loop
• S(i)
• C(i1)
• or (B(i) and C(i))
• end loop
• end process
• end arch1

For-loop defines multiple identical (or similar)
sub-circuits. Loop does not imply sequential
ordering of signal assignments.
Note separate carry signal for each stage
cannot re-assign values to one signal as in
sequential programs.
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Case Statement

• Case statement provides convenient way to express
  alternatives that depend only on value of a
  single signal
• architecture a1 of foo is
• begin
• process(c,d,e) begin
• b
• case e is
• when "00" a
• when "01" a
• when "10" a
• when others a
• end case
• end process
• end a1
• Creates more efficient circuits than equivalent
  if-then-else.

others alternative is required even when all
logical alternatives are specified
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VHDL Spec. for Simple Arithmetic Unit
entity alu is Port ( a, b in
std_logic_vector(3 downto 0) c in
std_logic_vector(2 downto 0) x out
std_logic_vector(3 downto 0) v out
std_logic) end alu architecture a1 of alu
is signal result std_logic_vector(4 downto
0) signal ax, bx std_logic_vector(4 downto
0) begin ax "001" else (not ax)1 when c "010"
else (not bx)1 when c "011"
else axbx when c "100" else axbx when
c "101" else ax-bx when c "110"
else bx-ax x '1 when (c "010" and a "1000") or (c
"011" and b "1000") or (c "100" and
result(4) '1') or (c "101" and a(3) b(3)
and a(3) / result(3)) or (c "110" and
a(3)/b(3) and a(3) / result(3)) or (c
"111" and a(3)/b(3) and b(3) /
result(3)) else '0' end a1
c0 means xa, c1 means xb, c2 means x -a,
c3 means x-b, c4 means xab (unsigned), c5
means xab (signed), c6 means xa-b, c7 means
xb-a
v bit signalsarithmetic error
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VHDL Spec. for ALU with Generics
entity alu is Port ( a, b in
std_logic_vector(wSiz-1 downto 0) c
in std_logic_vector(ctlSiz-1 downto 0)
x out std_logic_vector(wSiz-1 downto 0)
v out std_logic) end alu architecture a1
of alu is signal result std_logic_vector(wSiz
downto 0) signal ax, bx std_logic_vector(wSiz
downto 0) begin ax b with c select result , bx when "001" , (not ax)1 when "010"
, (not bx)1 when "011" , axbx when
"100" , axbx when "101" , ax-bx when
"110" , bx-ax when others x result(wSiz-1 downto 0) v "010" and a "1000") or (c "011" and b
"1000") or (c "100" and result(wSiz)
'1') or (c "101" and a(wSiz-1) b(wSiz-1)
and a(wSiz-1) / result(wSiz-1)) or (c "110"
and a(wSiz-1)/b(wSiz-1) and a(wSiz-1) /
result(wSiz-1)) or (c "111" and
a(wSiz-1)/b(wSiz-1) and b(wSiz-1) /
result(wSiz-1)) else '0' end a1
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Alternate Architecture

• architecture arithuv_arch of arithuv is
• signal result STD_LOGIC_VECTOR(4 downto 0)
• signal ax, bx STD_LOGIC_VECTOR(4 downto 0)
• signal en_a, en_b, neg_a, neg_b STD_LOGIC
• begin
• process(a,b,c,en_a,en_b,neg_a,neg_b) begin
• en_a
• v
• case c is
• when "000" en_b
• when "001" en_a
• when "010" en_b
• if a "1000" then v
• when "011" en_a
• if b "1000" then v
• when "100" v
• when "101" if a(3) b(3) and result(3) /
  a(3) then
• v
• end if

case statement specifies alternatives based on
signal value.
en_a high when a used to generate result. neg_a
high to produce -a or b-a.
others required when not all alternatives listed.
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for i in 0 to 3 loop ax(i) neg_a) and en_a bx(i) en_b end loop ax(4) neg_a) bx(4) neg_b) result x arithuv_arch
for-loop modifies a, b
extend a, b to 5 bits with correct sign

• Original architecture synthesizes redundant
  components.
• Alternative architecture uses single adder and
  disables or negates inputs to implement different
  operations.
• circuit uses about half as many circuit
  components as original
• synthesis report provides detailed description

21
Structural Spec. for 4 Bit Adder

• entity adder4 is port(
• A, B in std_logic_vector(3 downto 0) Ci in
  std_logic S out std_logic_vector(3 downto
  0) Co out std_logic)end adder4architecture
  a1 of adder4 iscomponent fullAdder
• port(A, B, Ci in std_logic S, Co out
  std_logic )end componentsignal C
  std_logic_vector(4 downto 0)begin
• C(0)
• b0 fullAdder port map(A(0),B(0),C(0),S(0),C(1))
  b1 fullAdder port map(A(1),B(1),C(1),S(1),C(2))
  b2 fullAdder port map(A(2),B(2),C(2),S(2),C(3)
  ) b3 fullAdder port map(A(3),B(3),C(3),S(3),C(4
  ))
• end a1

Component definitions required in every
architecture using a component.
component statement used to form complex circuits
from simpler parts.
Positional association of signals. Explicit
assignment (AA(0)) also allowed.
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Defining Constants

• To define constants for use by multiple entities,
  use separate package.
• package commonConstants is
• constant wordSize integer 8
• end package commonConstants
• library IEEE
• use IEEE...
• use work.commonConstants.all
• entity adder is
• port( A, B in std_logic_vector(wordSize-1
  downto 0)
• Ci in std_logic
• S out std_logic_vector(wordSize-1 downto
  0)
• Co out std_logic )
• end adder
• ...
• Local constants can be declared as part of each
  architecture.
• HDL bencher does not handle constants in packages
  correctly.
• use Options ?Map Package Constants/Defines

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Structural Specs. using for-generate

• begin C(0) b fulladder port map(A(i),B(i),C(i),S(i),C(i1)
  ) end generate
• Co

for-generate makes it easy to generate adder of
any size. Note labels are required.