Fault Coverage Analysis of RAM Test Algorithms

1
Fault Coverage Analysis of RAM Test Algorithms

• Marc Riedel
• McGill University, Montreal, Canada
• Janusz Rajski
• Mentor Graphics, Wilsonville, Oregon

2
Outline

• Motivation
• Fault Models
• Methodology and Complexity
• Fault Simulation Results
• Conclusions

3
Motivation

• Functional Memory Testing
• A multitude of fault models and test schemes
  proposed.
• Quality of fault coverage difficult to assess.

• Coverage Measures Needed

• To evaluate and rank existing test algorithms
• Deterministic/regular tests.
• Pseudo-random/irregular tests.

• To validate new test schemes for
• Embedded memories and BIST designs.
• Specialized memory architectures (e.g.,
  multiport, FIFO).

4
Functional Cell Array Model

• Bit-addressable 2-D array of binary storage
  elements

...
Operations read, write-0, write-1.
5
Functional Fault Behavior

• Sensitized/desensitized by write operations.
• Detected by read operations.

write
Sensitized
Unsensitized
read
Detected
0 / 1
write
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Cell Array Fault Models
stuck-at, transition, stuck-open, data-retention
Single Cell
idempotent, inversion, state, dynamic (2-cell and
3-cell versions)
Coupling
AND-type, OR-type (2-cell and 3-cell versions)
Bridging
active, passive, static (type I and type II
neighborhoods)
Neighborhood Pattern Sensitive
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Fault Model Specification

• Fault models are specified as inputs, not
  hard-coded.

Example
Format
sensitization
lt write op. gt
lt mem. pattern gt
lt write op. gt
lt mem. pattern gt
desensitization
lt write op. gt
lt mem. pattern gt
lt write op. gt
lt mem. pattern gt
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Ex. 2-cell OR-type Bridging Fault
Operation
a
b
sensitization
write-1, a
0
0
write-1, b
0
0
a
b
write-0, a
1
1
write-0, b
1
1
read to either cell returns OR(a,b)
desensitization
write-0, a
1
0
write-0, b
0
1
write-1, a
0
1
write-1, b
1
0
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Coverage Analysis
Simulation performed for arbitrary test sequences.
case write
write-1,
lt add. gt
read,
lt add. gt
Determine which faults are sensitized or
desensitized.
write-0,
lt add. gt
write-1,
lt add. gt
case read
read,
lt add. gt
.
.
Classify all sensitized faults as covered.
.
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Sensitization Desensitization
A write operation can sensitize/desensitize
several faults.
Example
active NPSF
3
3
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Delayed State Transitions
Sensitization/desensitization occur after a time
delay
Used to model retention faults, e.g.,
"sleeping-sickness" failures in DRAMS
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Multiple Faults
Error masking
Multiple sensitizations
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Multiple Faults (cont.)

• Sensitized faults change the memory pattern.
• This affects the sequence of sensitization/desensi
  tization of other faults.

Example
no faults sensitized
fault A sensitized
faults A and B sensitized
fault B sensitized
1
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
1
0
A
C
A
C
A
C
1
1
1
1
1
1
1
1
0
B
B
B
?
the pattern surrounding cell C is all 1s ??a
sleeping-sickness fault is sensitized
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Complexity
with respect to the test sequence length t
NPSFs
with respect to the neighborhood size k
k-cell coupling faults
with respect to the memory size n number of
coupled cells k
NPSFs cells in physical proximity.
Coupling faults cells located anywhere in memory
array.
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Examples of Test Algorithms
March X
March C-
GALPAT
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Simulation Results for March X
256-bit memory (16 rows x 16 columns)
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Simulation Results for March C-
256-bit memory (16 rows x 16 columns)
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Simulation Results for GALPAT
256-bit memory (16 rows x 16 columns)
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Trace of Simulation for ANPSF Test
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Conclusions

• General RAM fault simulation methodology.

• Library of over 25 functional fault models.

• Coverage statistics for over 40 test algorithms.

Application

• Evaluation of arithmetic BIST schemes for
  memories.