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FABRICATION OF SILICON

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Title: FABRICATION OF SILICON


1
FABRICATION OF SILICON ON INSULATOR (SOI)
DONE BY, A.POOJA SHUKLA ECE B
(190912066) SAVEETHA UNIVERSITY
2
AIM
  • To fabricate PHOTONIC CRYSTAL in SOI.
  • To use 248-nm deep UV Lithography for
    fabrication.
  • To use metal-oxide-semiconductor process.

3
ABSTRACT
  • Demonstration of wavelength-scale photonic
    nanostructures, including PHOTONIC CRYSTALS.
  • Fabrication of silicon on insulator using deep UV
    Lithography.
  • Comparing UV lithography with E-BEAM lithography.

4
INTRODUCTION
  1. Overview of photonic crystals, using deep UV
    Lithography.
  2. Use in optical waveguides.
  3. Current Lithography techniques for fabrication of
    PICs.

5
PROCESS INVOLVED
  1. PHOTONIC CRYSTALS
  2. SOI FOR INTEGRATED OPTICS
  3. LITHOGRAPHY FOR PHOTONIC CRYSTALS
  4. FABRICATION
  5. LITHOGRAPHY ISSUES

6
1. PHOTONIC CRYSTALS
  • PHOTONIC CRYSTALS are periodic optical
    nanostructures that are designed to affect the
    motion of photons in a similar way that
    periodicity of a semiconductor crystal affects
    the motion of electrons.
  • They have separate high dielectric and low
    dielectric regions.
  • Periodic spacing for relevant light frequency.

7
ADVANTAGE OF PHOTONIC CRYSTAL
  • Reduce Band Gap
  • Reduce defects
  • example if there is a LINE DEFECT in
    structure, it will act as a waveguide
  • Avoids Propagation of a Material

8
CONSTRUCTION STRATEGIES
  • The fabrication method depends upon the number of
    dimensions that the photonic band gap must exist
    in.
  • 1-D Photonic Crystals
  • 2-D Photonic Crystals
  • 3-D Photonic Crystals

9
PHOTONIC CRYSTAL SLAB
  • Any type of dimension can be used.
  • High refractive index contrast gives high
    diffractive property.
  • PBG bounds defects in crystal.
  • Completely lossless and allows short bends
    without radiation loss.

10
2. SOI FOR INTEGRATED OPTICS
  • SOI was first used in CMOS application to reduce
    the parasitary capacitance to the silicon
    substrate.
  • The top layer of SI acts as an optical waveguide
    due to high vertical index contrast.
  • SOI uses large cores i.e., top SI layers of upto
    10um thick but we use 205nm.
  • SOI wafer bonding of a buried oxide is 400nm.
  • Due to leakage slab waveguide remains single
    mode for a silicon thickness upto 268nm.
  • The minimum loss of 6 db/mm.

11
SILICON LAYER THICKNESS CHART
12
3. LITHOGRAPHY FOR PHOTONIC CRYSTALS
  • Photolithography (or "optical lithography") is a
    process used in microfabrication to selectively
    remove parts of a thin film or the bulk of a
    substrate.
  • It uses light to transfer a geometric pattern
    from a photomask to a light-sensitive chemical
    "photoresist", or simply "resist," on the
    substrate.
  • For example, in complex integrated circuits, a
    modern CMOS wafer will go through the
    photolithographic cycle up to 50 times

13
GENERAL COMPARISON
  • E-BEAM
  • DEEP UV
  • Size within 10nm.
  • Most used for research purpose.
  • Structure is not defined.
  • Defines extremely small features.
  • Not suitable for large volume because the process
    is very slow.
  • Size of any illuminated wavelength.
  • Widely used for CMOS fabrication.
  • Mostly used for structure defining.
  • Reduced wavelength become fuzzy.
  • High end deep lithography

14
4. FABRICATION
  • Steps involved in the fabrication of the PHOTONIC
    CRYSTALS are given below,
  • FABRICATION PROCESS
  • 1. Lithography
  • 2. Etching
  • DENSE SQUARE LATTICES
  • SUPERDENSE TRIANGULAR LATTICES

15
FABRICATION PROCESS
1. LITHOGRAPHY



16
  • The deep uv lithography facilities we use
    5500/300 deep uv stepper with an illumination
    wavelength of 248 nm.
  • The stepper uses 200 nm wafers.
  • It is used in resist coating, baking, and
    development.
  • Steps for lithography,
  • 1. Wafer illuminated in stepper
  • 2. Post exposure bake resist
    impurity is removed
  • 3. Development

17
2. ETCHING
The etching of the SOI wafer is done using a
double etch, in different chambers
18
TOP AND BOTTOM VEIW OF SILICON ETCHING
  • No air is exposed when two chambers are etched.
  • The top layer of silicon is etched using LOW
    PRESSURE and HIGH DENSITY.
  • The top layer of silicon can be replaced by
    AMORPHOUS SILICON.

19
DENSE SQUARE LATTICES
20
  • The first lithography test were carried out
    using a CMOS process evaluation mask with dense
    contact holes.
  • For perfect crystal we expose LARGER HOLES but
    SAME PITCH (400 to 600 nm), ratio is (0.25 to
    0.35).
  • Vertical sidewalls show roughness in square
    lattices so we prefer SUPERDENSE TRIANGULAR
    LATTICES

21
SUPERDENSE TRIANGULAR LATTICES
22
  • The triangular lattice provides various pitch
    and hole size, both in top-down and cross-section
    view.
  • Holes are very uniform through out the lattice.
  • There is an strong effect of side lobes from the
    crystal wall.

23
5. LITHOGRAPHY ISSUES
  • A common problem in dense structures are,
  • The size and shape of a structure is changed
    with the presence of a neighboring structures.
  • The various structures on photonic Ics each
    require different lithography conditions.
  • The effects are,
  • (a) Optical Proximity
    Effects
  • (b) Line Hole Bias

24
OPTICAL PROXIMITY EFFECTS
BASIC PRINCIPLE
  • Photonic crystals are superdense periodic
    structures with feature sizes close to the
    illumination wavelength.
  • During lithography, neighboring holes interfere
    with eachother.
  • Due to this the holes get larger or smaller
    during the print.
  • This phenomenon is called as OPTICAL PROXIMITY
    EFFECTS (OPE).

25
EFFECT IN SUPERDENSE LATTICE
  • The denser the structures and the smaller the
    pitch, the stronger the OPE becomes

26
  • The border holes are smaller than the holes in
    the bulks.
  • The hole in the inner corner prints more smaller
    than the border holes.
  • EXAMPLE
  • When the OPE of the
    lattice with a relatively large pitch of 530 nm,
    but with holes targeted at 420 nm.

27
LINE HOLE BIAS
  • Different geometrics are on the same level of
    the chip, and preferably printed together.
  • Small holes needs a much higher illumination
    than the larger holes i.e, a few hundreds of nm
    in width.

28
RESULTS
  • The new mask structures should be included to
    study the effect of OPE in photonic crystals.
  • The lithography should target the features with
    the highest exposure.
  • The bias should be applied on the mask to the
    features that need less energy to print on target.

29
CONCLUSION
  1. Deep uv lithography has potential for the mass
    fabrication of ultra compact photonic Ics based
    on photonic crystal.
  2. SOI shows well defined holes with very little
    edge roughness.
  3. The neighboring of the holes can be avoided by
    using OPTICAL PROXIMITY CORRECTION (OPC) method.
  4. Thus, deep uv lithography is suitable for
    providing mass-manufacturing capabilities to the
    ultracompact photonic Ics.

30
REFERENCES
  • Fabrication of photonic crystals in SOI using
    248 nm deep uv lithography, IEEE.
  • SOI Photonic Crystal Fabrication Using Deep UV
    Lithography, IEEE.
  • www.google.com
  • www.wikipedia.com

31
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