Advanced Digital Circuits ECET 146 Week 1

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Advanced Digital CircuitsECET 146Week 1

• Professor Iskandar Hack
• ET 205B, 481-5733
• hack_at_ipfw.edu

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Weeks Goals

• Course Overview
• Overview of Embedded Digital Systems
• Overview of Digital Technologies
• Overview of Design Entry Techniques

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Goals of Course

• Understanding of basic concepts of programmable
  logic
• Understand various types of programmable logic
  devices such as Field Programmable Gate Arrays,
  Masked Gate Arrays, Standard Cell, and Full
  Custom Chips
• To be able to use an industry standard digital
  design package such as Alteras Max Plus or
  Xilinxs ISE Foundation

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Goals of Course II

• Learn to use different design entry techniques,
  including schematic, waveform, state machine
  diagrams, and text hardware design languages
• Work in teams to solve complex design problems
• Present written and oral reports representing
  solutions to design problems

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Course Structure

• Course is project based 50 of your grade will
  be based upon successful completion of assigned
  projects in the laboratory.
• Quizzes there will be approximately ten quizzes
  that will be completed These will be open book,
  notes and most importantly youll want access to
  the Altera Quatrus software when you take them.
  The quizzes will be worth 10 of your final
  grade. (One point per quiz)

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Course Structure II

• Major projects there will be a Midterm and
  Final Project that will each count 20 of your
  course grade.
• Lab Teams Each Lab team will consist of two
  members. You are free to choose your own lab
  partner. However, each lab must be written by one
  member each time and alternate between lab
  members. You will need to identify which lab
  member is writing the report. The same is true
  with the midterm and final projects, however
  writes the midterm does not write the final
  report. You do not have to have a lab partner, if
  you desire you may work alone.

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Grades

• Grading is simple in this course You finish all
  of the assignments (ON TIME of course) and you
  receive an A.
• Of course if youre late, your lab reports dont
  meet the standard format, or your projects dont
  work then the final grade is adjusted.
• Most students that take this course will receive
  an A, those that dont are ones that dont finish
  the projects on time or they dont work.
• The primary reason that students do poorly is
  they wait until the project is due before they
  start working on it.

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Course Requirements

• Digital Electronics with VHDL by William Kleitz
  (same book as ECET 111)
• Altera Quatrus II II Design software (can be
  downloaded from www.altera.com or from course
  website)

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Additional Comments

• In order to transport your design files from home
  to the lab and to save your design files while
  working in the lab you will need to have either a
  USB-Flash drive. If you do all of your work on
  either a laptop that you carry back and forth or
  on the lab computers then you dont need the
  USB-Flash drive.
• NOTE there has been some minor problems with
  Flash drives losing data, be sure to back up
  regularly.

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Definition of an Embedded System

• An embedded digital system is any electronic
  system that uses digital logic as part of the
  control of the system.
• There are two fundamental types of embedded
  systems
• Microprocessor or Microcontroller based (covered
  in ECET 205/305)
• Custom Digital Logic (covered in this course)

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Types of Custom Digital Logic Devices

• Discrete Logic as covered in ECET 111
• Programmable Logic
• Simple Programmable Logic Devices
• Complex Programmable Logic Devices (CPLDs)
• Field Programmable Gate Arrays
• Masked Gate Arrays
• Standard Cell Custom Logic Integrated Circuits
• Full Custom Logic Integrated Circuits

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Simple Programmable Logic Devices

• These devices are also known as
• PAL (Programmable Array Logic)
• GAL (Generic Array Logic)
• PLA (Programmable Logic Array)
• PLD (Programmable Logic Device)
• SPLDs are the smallest and consequently the
  least-expensive form of programmable logic. An
  SPLD is typically comprised of four to 22 macro
  cells and can typically replace a few 7400-series
  TTL devices. Each of the macro cells is typically
  fully connected to the others in the device. Most
  SPLDs use either fuses or non-volatile memory
  cells such as EPROM, EEPROM, or FLASH to define
  the functionality.

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CPLD - Complex Programmable Logic Devices

• Also known as
• EPLD (Erasable Programmable Logic Device)
• PEEL
• EEPLD (Electrically-Erasable Programmable Logic
  Device)
• MAX (Multiple Array matriX from Altera)
• CPLDs are similar to SPLDs except that they are
  significantly higher capacity. A typical CPLD is
  the equivalent of two to 64 SPLDs. A CPLD
  typically contains from tens to a several hundred
  macro cells. A group of eight to 16 macro cells
  is typically grouped together into a larger
  function block. The macrocells within a function
  block are usually fully connected. If a device
  contains multiple function blocks, then the
  function blocks are further interconnected.

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CPLD - Complex Programmable Logic Devices II

• In concept, CPLDs consist of multiple PAL-like
  logic blocks interconnected together via a
  programmable switch matrix. Typically, each logic
  block contains 4 to 16 macrocells, depending on
  the architecture

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Layout of Standard CPLD
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Layout of Altera Max 7000 Family
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An Altera Max 7000 Macrocell
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Field Programmable Gate Arrays

• Similar to a CPLD, except the macrocells are
  smaller with respect to the overall device.
• There are far more macrocells and more
  interconnect inside a FPGA
• FPGAs can have several hundred thousand
  equivalent gates, and the number is increasing
  rapidly, and could be in the millions before
  long.

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Layout of a FPGA
I/O Blocks
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Masked Gate Array

• These are custom devices that must be ordered
  from an IC manufacturer
• They consist of a large number of either NAND or
  NOR gates that are not connected
• They are often referred to as a sea of gates
• The top layer mask is the interconnect that
  determines the final logic
• Remember from Basic Digital that ANY digital
  circuit (including FFs ) can be designed using
  just NAND or NOR gates

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Layout of a Mask Gate Array
I/O Blocks
Gate Array with Channels for interconnect
Gate Array without Channels
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Standard Cell Device

• Made up of standard Digital Logic cells such as
  counters, adders, multipliers memory components
  and even microcontrollers
• All mask layers are custom made
• Because of the need for all masks to be custom
  there is a long lead time for manufacturing and
  high cost for the fabrication of the masks

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Sample Layout of Standard Cell
Standard Cell Shift register
Gate Array With routing Chan.
Standard Cell adder
Input/Output
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Full Custom Device

• These are digital systems in which all parts of
  the design is done by hand for maximum
  performance or use of space
• The cost of designing such devices is extremely
  expensive
• Rarely used except in very high production units
  (several million units) or which absolute
  performance is necessary (military or space
  applications)

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Example of a Full Custom Device
80486 Chip from Intel
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Design Cost vs. Per Unit Cost

• Design Cost is the one time cost of designing
  the device, usually referred to as the NRE or
  Non-Recurring Engineering cost
• The per unit cost is the cost of each unit AFTER
  the NRE has been satisfied
• The Total Unit Cost (TUC) is equal to the
  (NRE)/( of Units) Per Unit cost
• It is important to compare TUC using available
  technologies to decide the appropriate technology
• There may be other reasons to use a particular
  technology such as security, power or size
  restrictions

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Example of Calculating Total Unit Cost

• The NRE is 125,000 for this particular design
• The Per Unit Cost is 1.35
• The Expected Number of units to be produced is
  325,000
• The Total Per Unit cost is (125000/325000) 1.35
  1.73 per device

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Comparison of Different Technologies
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Design Entry Techniques

• Schematic Designer draws the equivalent design
  using gates and other logic circuits (can include
  ICs such as JK FF or 74xxx parts)
• Waveform Design draws the desired input and
  output waveforms for the device
• State Machine Diagram Designer enters the
  design using a Finite State Machine Bubble
  Diagram
• Text Design Files Design specifies the design
  using a design language such as Altera Hardware
  Design Language (AHDL)

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Example of Schematic Design
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Example of Waveform Design
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Example of State Machine Bubble Graph
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Example of AHDL Design File
SUBDESIGN priority ( low, middle, high
INPUT highest_level1..0
OUTPUT --group,vector,bus ) BEGIN IF high
THEN --IF-THEN-ELSE statement
highest_level 3 --high -gt decimal 3 binary
11 ELSIF middle THEN highest_level
2 --middle -gt 10 ELSIF low THEN
highest_level 1 --low -gt 01 ELSE
highest_level 0 --no input was true -gt 00
END IF END
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Summary of Week 1

• Overview of the course
• Definition of Embedded Systems
• Microprocessor/Microcontroller
• Custom Digital Logic
• Technologies used in Custom Digital Logic
• Discrete Components
• Small Scale Programmable Logic
• Large Scale Programmable Logic
• CPLDs
• FPGAs
• Masked Gate Arrays
• Standard Cell
• Full Custom
• Design Entry Methods
• Schematic
• Waveform
• State Machine Bubble Graphs
• Text Design Files