Xilinx MGT Usage XC2VP7

1
Xilinx MGT Usage(XC2VP7)

• PCB Layout

2
WARNING!!!!!

• Pinouts not updated in this presentation. See
  schematic for correct pinouts.
• Cant find reference on metal layers. I found one
  a while back that said 6 layers were enough but
  the Virtex info says I need more layers. Trying
  to verify which is correct. For now Ive used M1,
  M2, M3, and M4 but that is just the metal layer
  order, not the actual metal layer. So M1 is above
  M2, and M2 is above M3, but M3 might actually be
  the forth metal layer. TBD.

3
Design Features

• General layout
• Xilinx chip
• Power isolation network ( power supply stuff)
• Passive (power) filtering
• Clock circuitry
• Optical transceiver
• Pin out
• Configuring the chip
• Board Simulations of critical traces (vias)
• Traces / High speed design board materials/plating

4
Riser Board with FG672 (V1)
13cm?

• Available I/O pins 396 (456 248 pins, 2.3 cm2)
• 400 pin VHDM-HSD daughter card connector w/ PWR
  module
• On-chip DCM (Digital clock manager)
• Optical transceiver clock from Xilinx
• JTAG connection
• Problem UWB B/W requirements need 16
  transceivers (XC2VP50)

7.62cm?
Optical transceivers
5.98cm
14.6cm
12.5cm
2.2cm
18.5cm?
Power networks
JTAG
Clock

















5
Riser Board with FG672 (V2)
13cm?
7.62cm?

• Problem? Need to mash power networks flatter or
  change their shape. Passive network capacitors
  must be located within 1cm of pin.
• About an inch of metal on sides of frame.

Optical transceivers
Power networks
JTAG
Clock
14.6cm
12.5cm
18.5cm?

















6
Riser Board with FG672 (V3)
13cm?
7.62cm?

• Problem? Approximately an inch from optical
  transceiver connectors (or ports or whatever
  theyre called) to frame wall.
• One solution Put cable connector openings so
  they face back at Xilinx chip. The cables would
  go over the top of the Xilinx chip.

Optical transceiver
Power networks
14.6cm
12.5cm
18.5cm?
Clock
JTAG
Optical transceiver

















7
D H board with FG672

• Ability to transmit and receive 32 bits. Here
  only using 24 bits
• The pin assignment shown on a later slide uses
  transceiver B bank and the counterclockwise pins
  from it. For the PROM to be here, transceiver A
  and the user I/Os on its counterclockwise side
  should be used.
• Only need two transceivers and optical
  transceivers

PROM
Clock
JTAG
Power networks
Optical transceiver
8
D H board with FG672

• Ability to transmit and receive 32 bits. Here
  only using 24 bits
• The pin assignment shown on a later slide uses
  transceiver B bank and the counterclockwise pins
  from it. For the PROM to be here, transceiver A
  and the user I/Os on its counterclockwise side
  should be used.
• Only need two transceivers and optical
  transceivers

Molex LaneLink Connector
4.89cm
Clock
PROM
JTAG
Power networks
Optical transceiver
9
D H board with FF896
7.6mm
1.25cm




1.25cm


PROM
Clock
6.5cm

JTAG

Power networks

Optical transceiver
10
Riser board with FG672
7.6mm
Decoupling caps can go on back
2.54cm
2.54cm
1.25cm
Optical transceiver
Power networks
Clock
JTAG
Optical transceiver
11
Component Sizes
12
Riser Board with FG1517 (XC2VP50)
13cm?

• Version 1
• Available pins 852 (1152 692 pins)
• Satisfies UWB B/W requirements. 16 MGTs
• Optical cables all go back over Xilinx chip
• Problem Wont fit inside frame

7.62cm?
PROM
14.6cm
12.5cm
18.5cm?
Clock
JTAG
2.2cm
5.98cm

















13
Riser Board with FG1517 (XC2VP50)
13cm?

• Version 2
• Still wont fit

7.62cm?
JTAG
5.98cm
14.6cm
12.5cm
18.5cm?
Clock
2.2cm

















14
Riser Board with FG1517 (XC2VP50)
13cm?

• Version 3
• Tight fit
• Use both sides of board?
• Give up and use two boards for UWB?

7.62cm?
14.6cm
12.5cm
18.5cm?
2.2cm
1.8cm

















15
Xilinx chip

• Transceiver
• Xilinx Virtex-Pro II P4 or P7 (P7 preferred)
• FF672 package (fine-pitch BGA)
• http//www.xilinx.com/products/virtex2pro/rocketio
  .htm
• Still under consideration

16
Power supply network for RocketIO
Vingt3VDC
Virtex Chip
2.5V_at_1.5A
AVCCAUXTX AVCCAUXRX VTTX VTRX GNDA
LT1963
100O
1?Fx10
330?F
VTT
GNDA
GNDA
93.8O
VTB
Power isolation
Bead and cap(0.22 ?F)
Supply can be shared among transceivers but each
supply pin needs own passive filtering network.
Passive filtering
17
RocketIO Power isolation

• Power isolation
• Linear Technology LT1963
• http//www.linear-tech.com/pub/q_srch.html?target
  LT1963pub_typeAllproduct_familyAllx18y9
• 1µF(10 in parallel), 330µF, 10µF, 100O, 93.8O
  required on side where MGTs are located

18
RocketIO Passive filtering for power supply pins

• Per power pin (Components cannot be shared)
• Capacitor 0.22µF
• 0603 SMT package of X7R dielectric material at
  10 tolerance, rated to at least 5V.
• Ferrite beads
• Murata BLM18AG102SN1
• http//www.murata.co.jp/cgi-spara/search.pl?primar
  yblm18

19
Optical transceiver
20
Parts Optical Transceiver

• Fiber optic transceiver
• Series four port RJ format optical transceiver
  for gigabit Ethernet or 1x fiber channel 3.3V,
  850nm VCSEL, Multimode, up to 550M
• See previous slide for parts
• http//www.stratoslightwave.com/PDF/89-R14K-ST11xx
  20.pdf
• Whats the difference between the one that goes
  to SerDes or Phys and LVPECL Phys or SerDes.

21
Clock network

• Choice of oscillators (frequency TBD (62.5MHz?))
• Epson EG-2121CA 2.5V (LVPECL outputs)
• http//www.eea.epson.com/go/Prod_Admin/Categories/
  EEA/QD/Crystal_Oscillators/all_oscillators/display
  Category
• Max of three 100O resistors. Need to match line.
  (7.0x5.0x1.4mm)
• Pletronics LV1145B (LVDS outputs)
• http//www.pletronics.com/LV1100B.htm
• Max of one 100O resistor. Need to match line.
• Cable?
• ?Circuitry isnt that much different. Example
  found using oscillator.

22
DCM and clocks

• Data width is set by ratios of two clocks inputs
• For REFCLK62.4 MHz, 4-bytes will be sent on
  1.25GHz.

23
Data needs

• UWB and MCMA issues

24
UWB data transmission
Transmitter 0 Transmitter 1 Transmitter
2 Transmitter 3 Transmitter 4 Transmitter
5 Transmitter 6 Transmitter 7 Transmitter
8 Transmitter 9 Transmitter 10 Transmitter
11 Transmitter 12 Transmitter 13 Transmitter
14 Transmitter 15
Data 0 (8-bits)
Data 1 (8-bits)
Data 2 (8-bits)
Data 3 (8-bits)
Data 4 (8-bits)
Data 5 (8-bits)
Data 6 (8-bits)
Data 7 (8-bits)
Data 8 (8-bits)
Data 9 (8-bits)
Data 10 (8-bits)
Data 11 (8-bits)
Data 12 (8-bits)
Data 13 (8-bits)
Data 14 (8-bits)
Data 15 (8-bits)
25
UWB data transmission(8-bitsx2.4Gbs
?128-bitsx156.25MHz)
Transmitter 0 Transmitter 1 Transmitter
2 Transmitter 3 Transmitter 4 Transmitter
5 Transmitter 6 Transmitter 7 Transmitter
8 Transmitter 9 Transmitter 10 Transmitter
11 Transmitter 12 Transmitter 13 Transmitter
14 Transmitter 15
26
DCM configurations

• 4-byte clock
• 4 DCMs per P4, P7(http//direct.xilinx.com/bvdocs/
  publications/ds083-1.pdf)

CLKDIV2
BUFG
IBUFGDS
MGT input inverters. Acceptable skew
27
Power Needs (Low)
www.xilinx.com/ise/power_tools/spread_sheet_pt.htm
28
Parameters for Power Estimate (Low)
29
Parameters for Power Estimate (Low)
30
Power Regulator Parts (Low)
31
Power Needs (High)
www.xilinx.com/ise/power_tools/spread_sheet_pt.htm
32
Parameters for Power Estimate (High)
33
Parameters for Power Estimate (High)
34
Parameters for Power Estimate (High)
35
Power regulator (High)

• Using the 2X rule
• Need 11.2W for MCMA
• Take 1.6 W from Sues source for 3.3V supply
• 1.8 W from 2.5V source
• 7.8 W from 1.5V source

36
Power Regulator Parts (High)
37
Power FF896 (High)
38
Parameters for Power Estimate (896 High)
39
Power Regulator Parts(896 High)
40
1.5V Voltage Regulator

• TI Low Dropout voltage regulator
• TO-220 (KC) TPS75915KC
• http//focus.ti.com/docs/prod/productfolder.jhtml?
  genericPartNumberTPS75915

41
Percent of pins used (Vcco pins)

• Bank 2, 3, 6, 7 (2.5V, 3.3V)
• Bank 2/3/6/7 outputs 64
• SSO 8 per VCC/GND pair?? (LVTTL16_fast)
• GND/Vcco pairs 6
• Limit SSOVcco48
• Outputs 64
• Percentage of budget used 64/48133 (Number of
  pins used61338 pins)
• Bank 0,1,4 5 (2.5V, 3.3V)
• Bank 0/1/4/5 outputs 35
• SSO 8 per VCC/GND pair?
• GND/Vcco pairs 6
• Limit SSOVcco48
• Outputs 35
• Percentage of budget used 35/4873 (Number of
  pins used6455 pins)

42
Quantity of caps Banks 0-3(Per Vcco pins 3.3V)
43
Quantity of caps Banks 4-5(Per Vcco pins 2.5V)
44
Quantity of caps Banks 6-7(Per Vcco pins
2.5V/3.3V)
45
Percent of pins used (Vcint pins)

• Vcint (1.5V)
• Pins 24
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case and
  assume gt 80 will be used.

46
Quantity of caps(Per Vcint pins 1.5V)
47
Percent of pins used (Vccaux pins)

• Vcint (2.5V)
• Pins 12
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case.

48
Quantity of caps(Per Vccaux pins 1.5V)
49
Caps
50
Caps
51
FF896
52
Percent of pins used (Vcco pins)

• Bank 2, 3, 6, 7 (2.5V, 3.3V)
• Bank 2/3/6/7 outputs 84
• SSO 8 per VCC/GND pair?? (LVTTL16_fast)
• GND/Vcco pairs 11
• Limit SSOGND/Vcco pairs88
• Outputs 84
• Percentage of budget used 84/8896 (Number of
  pins used119611 pins)
• Bank 0,1,4 5 (2.5V, 3.3V)
• Bank 0/1/4/5 outputs 45
• SSO 8 per VCC/GND pair?
• GND/Vcco pairs 9
• Limit SSOVcco72
• Outputs 45
• Percentage of budget used 45/7263 (Number of
  pins used9636 pins)

53
Quantity of caps Banks 0-3, 7(Per Vcco pins
3.3V)
54
Quantity of caps Banks 4-5(Per Vcco pins 2.5V)
55
Quantity of caps Banks 6-7(Per Vcco pins
2.5V/3.3V)
56
Percent of pins used (Vccint pins)

• Vcint (1.5V)
• Pins 32
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case and
  assume gt 80 will be used.

57
Quantity of caps(Per Vcint pins 1.5V)
58
Percent of pins used (Vccaux pins)

• Vcint (2.5V)
• Pins 16
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case.

59
Quantity of caps(Per Vccaux pins 1.5V)
60
Caps
61
Caps
62
FF896 VII
63
Percent of pins used (Vcco pins)

• Bank 2, 3, 6, 7 (2.5V, 3.3V)
• Bank 2/3/6/7 outputs 84
• SSO 8 per VCC/GND pair?? (LVTTL16_fast)
• GND/Vcco pairs 11
• Limit SSOGND/Vcco pairs88
• Outputs 84
• Percentage of budget used 84/8896 (Number of
  pins used119611 pins)
• Bank 0,1,4 5 (2.5V, 3.3V)
• Bank 0/1/4/5 outputs 45
• SSO 8 per VCC/GND pair?
• GND/Vcco pairs 9
• Limit SSOVcco72
• Outputs 45
• Percentage of budget used 45/7263 (Number of
  pins used9636 pins)

64
Quantity of caps Banks 0-3(Per Vcco pins 3.3V)
65
Quantity of caps Banks 4-5(Per Vcco pins 2.5V)
66
Quantity of caps Banks 6-7(Per Vcco pins
2.5V/3.3V)
67
Percent of pins used (Vccint pins)

• Vcint (1.5V)
• Pins 32
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case and
  assume gt 80 will be used.

68
Quantity of caps(Per Vcint pins 1.5V)
69
Percent of pins used (Vccaux pins)

• Vcint (2.5V)
• Pins 16
• Since I dont know how many slices of the chip
  are going to be used, Ill assume worst case.

70
Quantity of caps(Per Vccaux pins 1.5V)
71
Caps
72
Caps
73
Other stuff

• All RocketIOs must be connected to power whether
  being used or not. Unused transceivers do not
  need special source or passive filtering circuit.
  Any 2.5 V source will work fine.

74
Havent had time to look up yet

• Any interconnect matching issues required for
  connecting the Xilinx chip to a trace or to a
  optical transceiver. Simulations of (critical
  traces).
• ToDo
• Power connections
• Change pinouts (456?672)
• Schematic

75
Motherboard for Intel RF FrontEndFloorplan
Connectorfor Power Supply
135
ADCLineDriver
A
Y
MatchingNetworkCircuitry
RXB
RXA
SCSI Connectorfor I/Q Data
RXB-11
Mixed-SignalFront-EndAD9862
TXQ
DACLineDriver
TXI
TXA
RXB-0
RXA-11
TXB
3468
Y
A
Intel 2.4-GHzFront-End
RXA-0
Connectorfor Control
Parallel RX TX lines
TX-0
RXI
TX-13
RXQ
ClkCircuitry
HS lines
OpticalIO
See following pages for pin assignments
Mounting Hole
SMA Connector
2003-02-21
76
Chip information

• FG456
• Fewer pins to mess with but enough of them to do
  what we need. (But cant use 32-bits on all
  transceivers on riser board. Only 248 user I/Os.
  FG672 has 396 user I/Os).
• Not chip used in demonstrations or LM300 (But
  available on AFX board)
• Pads
• NSMD (Non solder mask defined pads suggested)

77
Chip information

• FG672
• Need all 396 user I/Os.
• Pads
• NSMD (Non solder mask defined pads suggested)

78
Pinout (FG672)
Pin A1
Top view
Bottom view
79
Pinout D H (XC2VP4, P7 FG672)(Bottom view)
a Transceivers
Power (RocketIO) Clock (RocketIO)?? Transceiver1a,
1b (4, 21 Only P7) Transceiver2a, 2b (6,
19) Transceiver3a, 3b (7, 18) Transceiver4a, 4b
(9, 16 Only P7) Proposed Data I/O (644
pins) Global Clock Configuration ports (Port
names dont match configuration documentation)
b Transceivers
80
DH Pinout (XC2VP4, P7 FG676)
White pins are not usable for general I/O
RX 19 RX 17, 18 RX 14, 15 RX 13, 21 RX 11, 12,
22, 23 RX 9, 10, 24 RX 7, 8, 25, 26, 27, 28 RX
4, 5, 6, 29 RX 3, 30, 31 RX 2 RX 0, 1 TX 0, 1 TX
2, 3, 4 TX 5, 31 TX 6, 7, 30 TX 8, 9, 27, 28,
29 TX 10, 11, 26 TX 12, 13, 14, 25 TX 15, 24 TX
16, 17, 22, 23 TX 18, 19, 21 TX 20
M1 M2
To optical transceiver
81
DH Pinout (XC2VP4, P7 FG672)M1 (Bottom view)
RX 2b - C26 RX 1b - D26 RX 0b - E25 RX 15a -
E26 RX 14a - F25 RX 13a - F26 RX 12a - F24 RX 11a
- G26 RX 10a - H25 RX 9a - H26 RX 8a - J25 RX 7a
- J26 RX 6a - J24 RX 5a - K25 RX 4a - K26 RX 3a -
L25 RX 2a - L26 RX 1a - M25 RX 0a - N25 TX 0a -
P25 TX 1a - R25 TX 2a - R26XXX TX 3a - T25 TX 4a
- T26 TX 5a - U26 TX 6a - V25 TX 7a - V26 TX 8a -
V24 TX 9a - Y25 TX 10a - Y26 TX 11a - AA25 TX 12a
- AB25 TX 13a - AB26 TX 14a - AC25 TX 15a -
AD25 TX 0b - AD26 TX 1b - AE25 TX 2b - AE26 TX 3b
- AF26
White pins are not usable for general I/O
To optical transceiver
82
DH Pinout (XC2VP4, P7 FG672)M2 (Bottom view)
XX 5 - E23 XX 4 - E24 XX 3 F23 XX 2 - F24 XX 1
- G23 XX 0 - G24 RX 15b - H23 RX 14b - H24 RX 13b
- J23 RX 12b - J24 RX 11b - K23 RX 10b - K24 RX
9b - L22 RX 8b - L24 RX 7b - M23 RX 6b - M24 RX
5b - N23 RX 4b - N24 RX 3b - P23 TX 4b - P24 TX
5b - R23 TX 6b - R24 TX 7b - T23 TX 8b - T24 TX
9b - U23 TX 10b - U24 TX 11b - V23 TX 12b -
V24 TX 13b - W23 TX 14b - W24 TX 15b - Y23 XX 6 -
Y24 XX 7 - AA23 XX 8 - AA24 XX 9 AB23 XX 10
AB24 XX 11 AC24 XX 12 AD23
White pins are not usable for general I/O
To optical transceiver
83
DH Pinout (XC2VP4, P7 FG672)M4? (Bottom view)
XX 5 - E23 XX 4 - E24 XX 3 F23 XX 2 - F24 XX 1
- G23 XX 0 - G24 RX 15b - H23 RX 14b - H24 RX 13b
- J23 RX 12b - J24 RX 11b - K23 RX 10b - K24 RX
9b - L22 RX 8b - L24 RX 7b - M23 RX 6b - M24 RX
5b - N23 RX 4b - N24 RX 3b - P23 TX 4b - P24 TX
5b - R23 TX 6b - R24 TX 7b - T23 TX 8b - T24 TX
9b - U23 TX 10b - U24 TX 11b - V23 TX 12b -
V24 TX 13b - W23 TX 14b - W24 TX 15b - Y23 XX 6 -
Y24 XX 7 - AA23 XX 8 - AA24 XX 9 AB23 XX 10
AB24 XX 11 AC24 XX 12 AD23
White pins are not usable for general I/O
To optical transceiver
84
DH Pinout (XC2VP4, P7 FG672)M1 (Bottom view)
White pins are not usable for general I/O
HSRXB1N AF23 HSRXB1P AF22 HSTXB1N
AF21 HSTXB1P AF20 -- HSRXB2N AF18 HSRXB2P
AF17 HSTXB2N AF16 HSTXB2P AF15 CLKB0
AD14 CLKB1 AE14 CLKB2 AD13 CLKB3 AE13
HSRXB3N AF12 HSRXB3P AF11 HSTXB3N
AF10 HSTXB3P AF9 -- HSRXB4N AF7 HSRXB4P
AF6 HSTXB4N AF5 HSTXB4P AF4
85
DH Pinout (XC2VP4, P7 FG672)M2 (Bottom view)
White pins are not usable for general
I/O. Configuration signals on separate layer.
Global clocks on separate layer.
P1B1 AE23 P2B1 AD22 P3B1 AE22 P4B1
AE21 P5B1 AE20 -- -- P1B2 AE18 P2B2
AD17 P3B2 AE17 P4B2 AE16 P5B2 AE15 CLKB4
AB14 CLKB5 AC14 CLKB6 AB13 CLKB7 AC13 P1B3
AE12 P2B3 AD11 P3B3 AE11 P4B3 AE10 P5B3
AE9 -- -- P1B4 AE7 P2B4 AD6 P3B4 AE6 P4B4
AE5 P5B4 AE4
86
User I/O Pin table (Out of date)
87
System I/O Pin table (Out of date)
88
DH Pinout (XC2VP4, P7 FG672)Banks (Bottom
view)
25 23 21 19 17 15 13 11 9
7 5 3 1
89
Pinout (FG456)
Pin A1
Top view
Bottom view
90
Pinout D H (XC2VP4, P7 FG456)(Bottom view)
a Transceivers
A B C D E F G H J K L M N P R T U V W Y AA AB
b Transceivers
91
Pinout D H (XC2VP4, P7 FG456)M1? (Bottom
view)
RX1B15 D22 RX1B14 E20 RX1B13 E22 RX1B12
F21 RX1B11 F22 RX1B10 G21 RX1B9 G22 RX1B8
H20 RX1B7 H22 RX1B6 J21 RX1B5 J22 RX1B4
K21 RX1B3 K22 RX1B2 L20 RX1B1 L21 RX1B0
M20 TX1B0 M21 TX1B1 N21 TX1B2 N22 TX1B3
P20 TX1B4 P21 TX1B5 R21 TX1B6 R22 TX1B7
T21 TX1B8 T22 TX1B9 U20 TX1B10 U21 TX1B11
V21 TX1B12 V22 TX1B13 W21 TX1B14 Y21 TX1B15
Y22 TX1B15 Y22
A B C D E F G H J K L M N P R T U V W Y AA AB
92
Pinout D H (XC2VP4, P7 FG456)M2? (Bottom
view)
RX2B15 D21-- RX2B14 D21 RX2B13 E17 RX2B12
E19 RX2B11 F19 RX2B10 F20 RX2B9 G19 RX2B8
G20 RX2B7 H18 RX2B6 H19 RX2B5 J19 RX2B4
J20 RX2B3 K19 RX2B2 K20 RX2B1 L18 RX2B0
L19 TX2B0 M18 TX2B1 M19 TX2B2 N19 TX2B3
N20 TX2B4 P18 TX2B5 P19 TX2B6 R18 TX2B7
R19 TX2B8 T19 TX2B9 T20 TX2B10 U18 TX2B11
U19 TX2B12 V19 TX2B13 V20 TX2B14
W21-- TX2B15 Y21--
A B C D E F G H J K L M N P R T U V W Y AA AB
93
Pinout D H (XC2VP4, P7 FG456)M4? (Bottom
view)
Problem Final MCMA needs eight transceivers at
16-bits each. The FG456 could do max one 16-bit
and three 8-bit transceivers.
A B C D E F G H J K L M N P R T U V W Y AA AB
XX19 C13 XX18 C16 XX17 D14 XX16 D15 XX15
D16 XX14 E13 XX13 E14 XX12 E16 XX11
F13 XX10 F14 XX9 G18 XX8 J17 RX2B15
K18 TX2B15 K17 TX2B14 N17 XX7 N18 XX6
P17 XX5 T18 XX4 U13 XX3 U14 XX2 V13 XX1
W14 XX0 Y13
94
Pinout (XC2VP4, P7 FG456)
95
Pinout (XC2VP4, P7 FG456)First signal layer
Side Towards Optical Transceiver
96
DH Pinout (XC2VP20 FG896)Banks (Bottom view)
30 28 26 24 22 20 18 16 14 12
10 8 6 4 2
29 27 25 23 21 19 17 15 13
11 9 7 5 3 1
A B C D E F G H J K L M N P R T U V W Y AA AB AC A
D AE AF AG AH AJ AK
29 27 25 23 21 19 17 15 13
11 9 7 5 3 1
97
MGT Optical transceiver connections (Top
view)(XC2VP20 FG896)
4x180? to GND 100 ? between DiffPair (See
next slide)
98
MGT Optical transceiver connections (Top
view)(XC2VP20 FG896)
RDN RDP TDN TDP
Optical transceiver
39 37
33 31
29
GND
30 29 28 27 26 25 24 23
AK27 ? TX1N AK26 ? TX1P AK25 ? RX1P AK24 ? RX1N
4x180? to GND 100 ? between DiffPair (See
next slide)
Xilinx chip
99
Pinout

• High speed connections to MGT from optical
  transceiver (critical traces , impedance control
  traces ? simulation)
• RX/TX channel width at Xilinx output (12 I, 12 Q)
• Xilinx ? MCMA frontend
• 32-bits taken per RX and TX just in case
• Bit specification.
• Input and output FIFO commands

100
Chip configuration

• Methods
• Master Serial Mode, (Master SelectMAP Mode) (Chip
  loads itself at power-up)
• PROM (XC18V00) on board RX/TX basic configuration
• Configuration from off chip source
• JTAG or special configuration setup for RocketIO
• Configure from microprocessor
• Readback? ? Not needed

101
Configuration
102
JTAG Connector
103
6-pin JTAG Connection
104
Part names and labels