Interfacing External Memory

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Interfacing External Memory
Rajiv Nandivada
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High Level Schematic

• Clock cycle of 10-20 ns (Depending on its use).
• 3.3 V CMOS SRAM (128 x 8 bit).
• Uses multiplexed address and data bus to reduce
  the number of port pins. The lower
  address bits are held in latch while the data is
  transferred.

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Functional Block Diagram of SRAM

• Single 3.3 V supply.
• Lower power consumption via chip deselect.
• Available in 32 pin Plastic SOJ, and 32 pin Type
  II TSOP packages.

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Truth Table
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Pin Configuration
SOJ and TSOP Top View SOJ Small Outline J
Leads TSOP Thin Small Outline Package
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Characteristics
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Timing Diagrams
Read cycle
Write cycle
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Major Manufacturers of SRAM

• Alliance,
• Brilliance
• Crosslink
• Cypress Semiconductor
• Dense-PAC Micro
• Etron Technology
• Eureka
• Hitachi
• IBM
• IDT
• Mitsubishi
• NEC
• Samsung
• Seiko Epson
• Sharp
• Sony
• Toshiba

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Electrically Erasable Programmable Read-only
Memory (EEPROM)
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Erasable Programmable Read-only Memory (EPROM)
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Flash Memory
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I2C(Inter IC) Bus
SDA Serial Data Line SCL Serial Clock Line
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Packaging

• SOJ or Small Outline J-lead
• TSOP or Thin Standard Outline Package
• DIP or Dual Inline Package
• ZIP or Zigzag Inline Package
• PLCC or Plastic Leaded Chip Carrier

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Packaging Contd..

• SOJ or Small Outline J-lead
• TSOP or Thin Standard Outline Package
• DIP or Dual Inline Package
• ZIP or Zigzag Inline Package
• PLCC or Plastic Leaded Chip Carrier

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Pricing

• Depends on
• The type of package it comes in (DIP, SOJ, TSOP)
• The speed of the memory.
• The market value.
• The vendor (Digikey, Jameco)
• Storage capacity( 128K X 8, 256K X 8)
• The type of memory (Flash, EEPROM)

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References

• www.cygnal.com
• www.digikey.com
• www.srams.co.uk
• www.jameco.com
• www.atmel.com
• www.xicor.com