Receivers Design: Cases Studies

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Receivers Design Cases Studies

• Edgar Sánchez-Sinencio
• TI J. Kilby Chair Professor

Department of Electrical Engineering Analog and
Mixed-Signal Center Texas AM University http//am
esp02.tamu.edu/sanchez/
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Outline

• Brief Description of Receivers and Transceivers
  designed at the Analog and Mixed-Signal Center
  2000-2008 period
• Bluetooth
• System level design
• Building blocks design detail
• Dual standard Receiver Chamaleon
• Bluetoot and Wi-Fi ( 802.11b)
• Systems and Building block considerations

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Bluetooth Receiver
Chameleon Receiver
Radios Designed in AMSC 2000-2008
Ultra-Wideband Receiver
ZigBee Transceiver
Millimeter-wave Dual standard Receiver
MICS Transceiver
4
What research has been done on wireless systems
in AMSC ?

• Bluetooth Receiver in 0.35um CMOS technology.
  (2001-2002) 6 Ph.D. students and one faculty
  were involved.
• Chameleon Bluetooth/Wi-Fi (802.11b) Receiver in
  0.25um in SiGe IBM technology (2002-2003) 7
  Ph.D. students and one faculty were involved.
• Ultra Wide Band Receiver in 0.25um SiGe IBM
  technology (2004-2005) with 4 Ph.D. students and
  two faculty members were involved.
• Zigbee Transceiver in 0.18um TSMC (2004-2006)
  1 MSc and 6 Ph D and one faculty are involved
• MICS Transceiver in 0.13um UMC (2006-2008) 3
  Ph D students and two post-doctoral and one
  faculty are participating.

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What is Bluetooth?

• Bluetooth is a technology for small form factor,
  low-cost, short-range radio links between mobile
  PCs, mobile phones and other portable devices.

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Overview of Bluetooth

• 2.4GHz - 2.48 GHz ISM band.
• GFSK modulation index 0.28 - 0.35.
• 1 Mb/s data rate and 1 MHz channel spacing.
• The market size for Bluetooth chip to be 4.3
  billion by 2005 (Merrill Lynch)
• The Bluetooth special interest group has signed
  up 2491 member companies

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Bluetooth System Level Design
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Monolithic Receiver Architectures

• Direct-Conversion Receiver
• DC offset and flicker noise problem 99 of
  signal power is within DC to 430kHz.
• A fast settling AGC may be required for GFSK
  demodulation.

• Low-IF Receiver
• Greatly alleviated DC offset and Flicker noise
  problem.
• Relaxed image rejection requirement (33 dB).

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Potential Receiver Architectures Low IF
Receiver Architecture

• High level integration and possible low power
  design.
• Flicker noise less significant in signal band.
• DC offset can be easily removed.
• Image rejection.
• Folded-back interference.

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What other receiver structures alternatives can
be considered and with what properties ?
Can we make the IF very low, say to DC ? How and
at what price ?
Direct Conversion (IF0)
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Potential Receiver Architectures Direct
Conversion Receiver

• High level integration.
• No image rejection required.
• Less components, possible low power consumption
• DC offset.
• Flicker Noise.

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Which architecture to choose?

• Low IF is favored in specifications
• Image interference exception alleviates the image
  rejection requirement
• Flicker noise is hard to avoid in CMOS
  implementation
• Alternative technology (e.g. SiGe) may perform
  better with direct conversion architecture
• Low IF is the way to go for CMOS Bluetooth
  receiver!

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Problems to Solve in Low IF Receiver

• Choice of IF
• Trade-off between having relatively high or low
  IF should be taken into consideration
• Image rejection
• 9dB image signal need to be suppressed
• Folded-in interference rejection
• It could be worse interferer than image signal

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Problems to Solve in Low IF Receiver Trade-off
of IF

• Lower IF
• relaxed image rejection requirement
• lower folded back interference level
• lower Q requirement of the filter
• lower power consumption of baseband blocks
• Higher IF
• improved FM demodulator performance
• easily removed DC offset and less flicker noise
• 2 MHz IF is chosen for a good compromise.

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Image Rejection Active Complex Filter

• Not like the traditional nonlinear lowpass to
  bandpass frequency transformation, linear
  frequency transformation, H(jw) ---gt
  H(j(w-w0)obtain a complex bandpass filter.

5th Order Chebyshev Polypahse Filter
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Folded-in Interference

• Assuming IF is 2 MHz, a strong interference 5 MHz
  away from desired signal at RF is folded in to 1
  MHz away at IF. The interference can be 40 dB
  higher than the signal. Channel select filter
  stopband attenuation requirement can be stringent.

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Where is the Folded Interference ?

• Assuming IF is 2 MHz, a strong interference 5 MHz
  away from desired signal at RF is folded in to 1
  MHz away at IF. The interference can be 40 dB
  higher than the signal. Channel select filter
  stopband attenuation requirement can be stringent.

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Receiver Noise Figure and IIP3

• Receiver sensitivity -85 dBm
• Required SNR at baseband 15 dB
• Noise Bandwidth 1.35 MHz
• RF filter insertion loss 2.5 dB
• Receiver Noise Figure 10.2 dB
• Receiver IIP3 -14 dBm
• Power Consumption lt50 mA (3V supply)

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Complete Receiver Diagram
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Building Blocks DesignLNAMixerFrequency
synthesizer VCOActive complex filterLimiter
GFSK demodulatorDC offset tracking and canceling

• Low Noise Amplifier

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LNA Design Target

• Robust input matching
• 50 Ohm input impedance to provide the termination
  for preceding external compents
• High gain
• Since LNA is the first block of the entire
  receiver, high gain of the LNA helps to reduce
  overall noise figure
• Low noise
• Noise figure of LNA sets lower bound of the
  system noise figure
• Sufficient linearity, low power consumption

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Inductive Source Degeneration Type LNA
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On Chip Spiral Inductor

• On chip spiral inductor is utilized for source
  degeneration (Ls) and inductive load (Ld)
• Software ASITIC is used to characterize the on
  chip spiral inductor.

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Simulation ResultsGain and Noise

• Noise figure 2.6 dB
• Voltage gain 18.2 dB

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Building Blocks Design

• Mixer

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Mixer Design Consideration

• Different types of mixers are available
• Passive mixer lower power consumption
• Active mixer conversion gain reduces the
  requirement of LNA
• Low noise design is still important since mixer
  is one of the front end block
• Linearity requirement is higher than that of LNA

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Schematic of the mixer

• Double balanced Gilbert Cell mixer
• Current injection to alleviate the trade off
  between the linearity and power supply voltage

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Building Blocks Design

• Frequency Synthesizer

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Frequency Synthesizer Design Target

• Must be able to cover the entire band
• Minimize power consumption
• Make it as simple as possible integer-N type
• Settling time is relaxed in Bluetooth
  specification
• No need for more complex fractional-N type PLL
• The design of prescaler can be challenging since
  it has to work at carrier frequency

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The Synthesizer Structure

• An integer N architecture is preferred for the
  synthesizer to minimize power consumption
• Current steering logic prescaler
• Settling time 120ms
• Phase noise 130dBc_at_3MHz

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Prescaler Design

• Current steering dividers are used in the
  prescaler to reduce power consumption

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Synthesizer Simulations

• Settling time 120 ?s
• Complete PLL transistor level simulation

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Building Blocks Design

• Voltage Controlled Oscillator

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VCO Design Target

• Must be able to cover the entire band and some
  more to compensate process variation
• Quadrature (I/Q) output is required for
  modulation
• Tuning sensitivity must be high enough to cover
  the range but low enough to reduce noise due to
  control signal
• Phase noise requirement came from third and
  higher interference specifications

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VCO Schematics
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Discrete Tunable Bank Varactor

• The varactor has 2bit discrete tuning
• They can provide 4 steps of coarse tuning range
• Coarse tuning is mainly for compensating process
  variation

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Building Blocks Design

• Complex Filter

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How Does Complex Filter work?

• Bandpass filter for signal side, attenuator for
  image side

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How to implement complex filters?

• Design a LPF prototype by frequency shifting the
  desired BPF response to DC
• Frequency translation (s?s-jwc), by replacing
  each integrator by its complex equivalent

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How to implement complex filters?

• For OTA-C filters,
• two cross coupled
• OTAs are used
• Butterworth approximation
• is preferred because
• good group delay response
• all poles have the same magnitude
• Equal C design
• Equal cross coupled OTAs
• Good matching

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Complex Filter Design Target

• Image rejection depends on matching between I and
  Q branches (30dB image rejections requires 5
  gain error and 3o phase error).
• The LPF prototype is a 6th order Butterworth
  filter. The Corresponding BPF is 12th order.
• Due to the tough noise requirements, a very
  simple OTA is used.
• A simple input gain stage (15dB) is used to
  minimize the input referred noise
• Large channel lengths (6mm) are used to minimize
  flicker noise, improve matching, improve
  linearity, and avoid using cascode transistors.

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Complex Filter Overall Block Diagram

• 6th order Butterworth approximation
• Biquadratic OTA-C filter
• Automatic frequency tuning by relaxation
  oscillator

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Single BiQuad Stage
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OTA architecture

• gm is controlled by the common mode voltage.
• The CM voltage is stabilized using VCM
• VCM is controlled by the common mode detector at
  the input (CMFF) or the output (CMFB) of the OTA.

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Tuning Circuit

• Only frequency tuning is required since the
  maximum Q in the filter is 2, which is low enough
• The tuning circuit is run at 1MHz to minimize
  coupling to the complex filter

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Complex Filter Measurement

• Image Rejection Ratio 45dB
• Signal side attenuation 27dBc, 58dBc
• Image side attenuation-79dBc, -95dBc

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Building Blocks Design

• GFSK Demodulator

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Motivation to Build a Mixed-Mode Demodulator

• AGC difficult to handle in frequency hopping
  system.
• Short preample (4 symbols) requires extremely
  fast settling of AGC.
• Constant envelope GFSK modulation allow use of
  simple limiting receivers and non-coherent
  detection.
• By replacing AGC and ADC with a demodulator,
  power consumption can be lowered

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Mixed-Mode Demodulator

• So we turn to digital solution

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Digital Demodulator

• The information is contained in zero crossing
  point.
• Using rail-to-rail square wave eliminates the
  amplitude effect.
• The tunable one-shot at the output stage
  guarantee proper pulse width
• Sub-optimal detection

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Building Blocks Design

• Baseband

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Functions of the baseband signal processing
circuit

• Bit decision, obtain the bit stream based on the
  output of the demodulator.
• Track and compensate the DC offset caused by the
  LO frequency offset between receiver and
  transmitter and frequency drifting
• Generate the clock and control signal applied in
  the baseband signal processing circuit.

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Circuit Block Diagram

• DC offset tracking and holding circuit. Clock 1
  controls the integration of incoming signal,
  Clock 3 controls the update of DC offset and
  Clock 5 controls the offset cancellation
• Decision circuit. Clock 2 controls integrate and
  dump of the incoming signal, Clock 4 decides the
  decision timing.

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DC Offset Tracking Circuit

• During preamble and trailer, we integrate the
  signal to get an estimation of the DC offset
• After that we use a lowpass filter to track the
  DC changing in the coming signal.
• When ?4 is off, the circuit works as an
  integrator. When ?4 is on, it works as a lowpass
  filter.

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Track and Hold Circuit

• Fully differential architecture
• CMOS process has small leakage current that
  assures no extra circuit needed to compensate the
  voltage drop during holding period.
• ?3 is used to reset the voltage stored.

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Integrate and Dump Circuit

• Fully differential architecture
• ?4 is used to control the mode of the circuit.
  When it is high, the circuit is a preamp. When it
  is low, the circuit works as an integrator.
• ?3 is used to reset the capacitor.

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System Testing
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Die Photograph and PCB

• TSMC digital 0.35um process
• 6.25mm2

• 2.5mm

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Experimental ResultsSensitivity and BER Testing

• -82dBm sensitivity for 0.1 BER

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Experimental ResultsNoise

• 15dB Noise Figure

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Experimental ResultsLinearity (IIP3)

• -10dBm IIP3

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Conclusions on Bluetooth Receiver Design and
Testing

• Monolithic 3V Bluetooth receiver is realized
  using 0.35um digital process
• Developed independently in a university
  environment
• Feature active complex filter and mixed-mode GFSK
  demodulator
• 82dBm sensitivity and 10dBm IIP3
• 65mA current consumption from 3V supply
• 45mA expected with inductor with Q5

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The Team who developed and proposed the BT
Implementation.
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Design Implications of a Multistandard
Transceiver

• Share the maximum number or blocks possible
• Each block should comply with the most stringent
  specifications of both standards
• Tradeoffs between system integration and power
  consumption set the final architecture
• The design is not optimum for a particular
  standard, but meets the specifications of both

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Chameleon Receiver Timeline
Meeting Bluetooth 802.11b Standards
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Technology features

• IBM SiGe BiCMOS 6HP 0.25um
• Transit frequency (fT) 47GHz
• 6 aluminum metal layers
• Analog metal (4um thick, 0.00725 W/W)
• Varactor diode (intrinsic base-collector diode)
• Metal to metal cap (1.4fF/um2)
• MOS cap (3.115fF/um2)
• Poly resistors (21020, 360025 W/W)

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Standards Overview
Bluetooth 802.11b
Data rate 1Mb/s 1-11Mb/s
Power Lower Higher
Modulation FH-GFSK DSSS-CCK
Freq band 2.4 2.48GHz 2.4 2.48GHz
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Dual-Mode Receiver Architecture

• 3 possible alternatives for Bluetooth and Wi-Fi
  dual mode architectures

Low-IF and DCR
Low-IF and Low-IF
DCR and DCR
Area and power ? ? Sharing ? ? DC offset 1/f
noise ? ?
Power ? ? ? Sharing ? ?
Best fit for each standard ? Sharing ? ?
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Proposed Dual-Mode Architecture
Direct-conversion BT/WiFi receiver architecture
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Remarks

• Direct-conversion architecture is used for both
  standards to save power and avoid the image
  problem in IF architectures.
• LNA Mixer are shared between BT and Wi-Fi.
• Gm-C LPF with programmable bandwidth is used to
  accommodate both standards.
• Parallel Pipeline ADC architecture is used
• BT sampling rate 11MHz, 11bits
• Wi-Fi sampling rate 44MHz, 8bits
• Due to the short allowed settling time, the VGA
  has only two gain steps in BT mode and the signal
  level at the ADC input will vary by 24dB.
• In Wi-Fi mode, gain steps of 2dB are employed.

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Low Noise Amplifier

• Gain 15/-15dB
• NMOS drive is used for better linearity.
• Cm ensures matching in low-gain mode.

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I/Q Downconversion Mixer

• I Q share the same RF drive stage
• NMOS drive for better linearity
• NPN switch to reduce LO drive and 1/f noise

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Frequency Synthesizer

• VCO running at 2fo
• I/Q generation using divide-by-2 flip flop.
• Capacitor multiplier to integrate loop filter cap.

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Phase Switching Prescaler

• Phase switching prescaler for reduced power
• consumption compared with traditional
  architectures.
• No feedback in flip-flops.

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NF, IIP3, and IIP2 contributions
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Power consumption and area contributions
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• Programmable resolution and sampling rate.
• On line digital calibration.

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Receiver Die Photo
Deep Trench Isolation
3.8mm
5.6mm
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Testing Board
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Receiver Sensitivity

• Bluetooth -91dBm Wi-Fi (11Mb/s) -86.5dBm

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Test Procedure

• Connect 50W load at the input of LNA
• Set VGA gain at maximum
• Measure integrated noise at the output
• Connect signal generator
• Set amplitude such that the output corresponds to
  No SNRmin
• The amplitude of the generator corresponds to the
  sensitivity
• SNR signal level noise level

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Sensitivity Test
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Receiver Linearity
Both BT / Wi-Fi modes
IIP3 -13dBm
IIP2 10dBm
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Comparison Table
  1 1 2 2 This design This design
  BT WiFi BT WiFi BT Wi-Fi
Receiver Architecture Low-IF DCR Low-IF DCR DCR DCR
Offset cancellation Programmable loop Programmable loop Injection at AGC input Injection at AGC input AC coupling AC coupling
Channel select filter separate separate programmable programmable Programmable Programmable
Baseband amplifier separate separate shared shared Shared Shared
ADC Not included Not included Not included Not included Included Included
Filter bandwidth 1MHz (BPF) 7.5MHz (LPF) 1MHz (BPF) 7.5MHz (LPF) 600kHz (LPF) 6MHz (LPF)
Sensitivity -82dbm -88dBm -80dBm -92dBm (0dB SNR) -91dBm -86dBm
Technology 0.35 ?m CMOS 0.35 ?m CMOS 0.18 ?m CMOS 0.18 ?m CMOS 0.25?m BiCMOS 0.25?m BiCMOS
Rx active current 46mA 65mA 60mA 60mA 27.9mA (w/o ADC) 30mA (w/o ADC)
ADC active current - - - - 13.4mA 15.6mA
IIP3 -7dBm -8dBm -12dBm -12dBm -13dBm -13dBm
IIP2 N/A N/A 20dBm 20dBm 10dBm 10dBm
Rx area (w/ pads) N/A N/A 16mm2 (transceiver) 16mm2 (transceiver) 9mm2 (w/o ADC) 9mm2 (w/o ADC)
ADC area (w/ pads) - - - - 10mm2 10mm2
Supply voltage 2.7V 2.7V 1.8V 1.8V 2.5V 2.5V
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Summary Chamaleon Receiver

• Direct conversion architecture for BT / Wi-Fi
  allows maximum level of block sharing
• Lower consumption than previous dual-mode
  implementations (27.9 mA / 30mA)
• Shared RF front-end and programmable baseband
  components
• Programmable channel selection filter with
  constant linearity
• AC coupled VGA with constant output offset
• On-chip time interleaved pipeline ADC

88
References
1 W. Sheng, B. Xia, A.E.Emira, C. Xin, A.Y.
Valero-Lopez, S.T. Moon, and E.
Sanchez-Sinencio, A 3-V, 0.35 um CMOS Bluetooth
Receiver IC, IEEE J. of Solid-State
Circuits, Vol. 38, pp. 30-42, January 2003 2
B. Xia, C. Xin, W. Sheng, A.Y. Valero-Lopez, and
E. Sanchez-Sinencio, A GFSK Demodulator
for Low-IF Bluetooth Receiver, IEEE J.
Solid-State Circuits, Vol. 38, pp. 1397-1400,
August 2003. 3 A.A Emira,. E.Sánchez-Sinencio,
A pseudo differential complex filter for
Bluetooth with frequency tuning IEEE
Circuits and Systems II ,Volume 50, pp. 742 -
754 Oct. 2003 4 K. Shu, E. Sanchez-Sinencio,
J. Silva-Martinez, S.H.K. Embabi, S.H A 2.4-GHz
monolithic fractional-N frequency
synthesizer with robust phase-switching prescaler
and loop capacitance multiplier. IEEEJ.
of Solid-State Circuits, Vol. 38 , pp. 866-874,
June 2003. 5 A. Emira, A. Valdes-Garcia, B.
Xia, A. Mohieldin, A. Valero-Lopez, S. Moon, C.
Xin, and E. Sánchez-Sinencio, A
Dual-Mode 802.11b/Bluetooth Receiver in 0.25mm
BiCMOS, IEEE International Solid-State
Circuits Conference (ISSCC)I, pp. 270-271,527,
Wireless Consumer Papers, San Francisco,
CA, February 2004.
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Thank you for your attention
Any question ?
Analog and Mixed-Signal Center, TAMU Department
of Electrical and Computer Engineering