CS184a:%20Computer%20Architecture%20(Structure%20and%20Organization)

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CS184aComputer Architecture(Structure and
Organization)

• Day 6 January 22, 2003
• VLSI Scaling

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Today

• VLSI Scaling Rules
• Effects
• Historical/predicted scaling
• Variations (cheating)
• Limits

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Why Care?

• In this game, we must be able to predict the
  future
• Rapid technology advance
• Reason about changes and trends
• re-evaluate prior solutions given technology at
  time X.

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Why Care

• Cannot compare against what competitor does today
  
• but what they can do at time you can ship
• Careful not to fall off curve
• lose out to someone who can stay on curve

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Scaling

• Premise features scale uniformly
• everything gets better in a predictable manner
• Parameters
• l (lambda) -- Mead and Conway (class)
• S -- Bohr
• 1/k -- Dennard

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Feature Size
l is half the minimum feature size in a
VLSI process minimum feature usually
channel width
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Scaling

• Channel Length (L)
• Channel Width (W)
• Oxide Thickness (Tox)
• Doping (Na)
• Voltage (V)

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Scaling

• Channel Length (L) l
• Channel Width (W) l
• Oxide Thickness (Tox) l
• Doping (Na) 1/l
• Voltage (V) l

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Effects?

• Area
• Capacitance
• Resistance
• Threshold (Vth)
• Current (Id)
• Gate Delay (tgd)
• Wire Delay (twire)
• Power

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Area

• l ? l/k
• A L W
• A ? A/k2

• 0.35mm ? 0.25mm
• 50 area
• 2x capacity same area

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Area Perspective
2000 tech. 18mm?18mm 0.18mm 60G l2
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Capacity Scaling from Intel
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Capacitance

• Capacitance per unit area
• Cox eSiO2/Tox
• Tox? Tox/k
• Cox ? k Cox

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Capacitance

• Gate Capacitance
• Cgate ACox
• A ? A/k2
• Cox ? k Cox
• Cgate ? Cgate /k

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Threshold Voltage
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Threshold Voltage

• VTH? VTH /k

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Current

• Saturation Current
• Id(mCOX/2)(W/L)(Vgs-VTH)2
• VgsV? V /k
• VTH? VTH /k
• W? W/k
• Cox ? k Cox
• Id? Id/k

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Gate Delay

• tgdQ/I(CV)/I
• V? V /k
• Id ? Id/k
• C ? C /k
• tgd ? tgd /k

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Resistance

• RrL/(Wt)
• W? W/k
• L, t similar
• R ? k R

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Wire Delay

• twireR?C
• R -gt k R
• C -gt C /k
• twire -gt twire

• assuming (logical) wire lengths remain
  constant...
• Assume short wire or buffered wire
• (unbuffered wire ultimately scales as length
  squared)

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Power Dissipation (Static)

• Resistive Power
• PVI
• V? V /k
• Id? Id/k
• P? P /k2

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Power Dissipation (Dynamic)

• Capacitive (Dis)charging
• P(1/2)CV2f
• V? V /k
• C ? C /k
• P? P/k3

• Increase Frequency?
• f ? kf ?
• P ? P/k2

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Effects?

• Area 1/k2
• Capacitance 1/k
• Resistance k
• Threshold (Vth) 1/k
• Current (Id) 1/k
• Gate Delay (tgd) 1/k
• Wire Delay (twire) 1
• Power 1/k2? 1/k3

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ITRS Roadmap

• Semiconductor Industry rides this scaling curve
• Try to predict where industry going
• (requirementsself fulfilling prophecy)
• http//public.itrs.net

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MOS Transistor Scaling(1974 to present)
from Andrew Kahng
Source 2001 ITRS - Exec. Summary, ORTC Figure
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Half Pitch ( Pitch/2) Definition
from Andrew Kahng
Source 2001 ITRS - Exec. Summary, ORTC Figure
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Scaling Calculator Node Cycle Time
from Andrew Kahng
Source 2001 ITRS - Exec. Summary, ORTC Figure
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from Andrew Kahng
Source 2001 ITRS - Exec. Summary, ORTC Figure
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Delays?

• If delays in gates/switching?
• If delays in interconnect?
• Logical interconnect lengths?

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Delays?

• If delays in gates/switching?
• Delay reduce with 1/k l

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Delays

• Logical capacities growing
• Wirelengths?
• No locallity?k (slower!)
• Rents Rule
• L ? n(p-0.5)
• pgt0.5

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Compute Density

• Density compute / (Area Time)
• k3gtcompute density scalinggtk
• k3 gates dominate, plt0.5
• k2 moderate p, good fraction of gate delay
• p from Rents Rule again more on Day12
• k large p (wires dominate area and delay)

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Power Density

• P-gt P /k2 (static, or increase frequency)
• P-gt P/k3 (dynamic, same freq.)
• A -gt A/k2
• P/A ? P/A or P/kA

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Cheating

• Dont like some of the implications
• High resistance wires
• Higher capacitance
• Need for more wiring
• Not scale speed fast enough

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Improving Resistance

• RrL/(Wt)
• W? W/k
• L, t similar
• R ? k R

• Dont scale t quite as fast.
• Decrease r (copper)

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Improving Capacitance

• Capacitance per unit area
• Cox eSiO2/Tox
• Tox? Tox/k
• Cox ? k Cox

Reduce Dielectric Constant e
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Wire Layers More Wiring
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Typical chip cross-section illustrating hierarchic
al scaling methodology
Passivation
Dielectric
Wire
Etch Stop Layer
Via
Global (up to 5)
Dielectric Capping Layer
Copper Conductor with Barrier/Nucleation Layer
Intermediate (up to 4)
Local (2)
Pre Metal Dielectric
Tungsten Contact Plug
from Andrew Kahng
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Improving Gate Delay

• tgdQ/I(CV)/I
• V? V /k
• Id(mCOX/2)(W/L)(Vgs-VTH)2
• Id ? Id/k
• C ? C /k
• tgd ? tgd /k

Dont scale V V?V I?kI tgd ? tgd /k2

• Lower C.
• Dont scale V.

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But Power Dissipation (Dynamic)

• Capacitive (Dis)charging
• P(1/2)CV2f
• V? V /k
• C ? C /k
• P? P/k3

• Increase Frequency?
• f ? kf ?
• P ? P/k2

If not scale V, power dissipation not scale.
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AndPower Density

• P? P (increase frequency)
• P?gt P/k (dynamic, same freq.)
• A ? A/k2
• P/A ? kP/A or k2P/A
• Power Density Increases

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Physical Limits

• Doping?
• Features?

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Physical Limits

• Depended on
• bulk effects
• doping
• current (many electrons)
• mean free path in conductor
• localized to conductors
• Eventually
• single electrons, atoms
• distances close enough to allow tunneling

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What Is A Red Brick ?

• Red Brick ITRS Technology Requirement with no
  known solution
• Alternate definition Red Brick something
  that REQUIRES billions of dollars in RD
  investment

from Andrew Kahng
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The Red Brick Wall - 2001 ITRS vs 1999
Source Semiconductor International -
http//www.e-insite.net/semiconductor/index.asp?la
youtarticlearticleIdCA187876
from Andrew Kahng
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Finishing Up...
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Big IdeasMSB Ideas

• Moderately predictable VLSI Scaling
• unprecedented capacities/capability growth for
  engineered systems
• change
• be prepared to exploit
• account for in comparing across time

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Big IdeasMSB-1 Ideas

• Uniform scaling reasonably accurate for past
  couple of decades
• Area increase k2
• Real capacity maybe a little less?
• Gate delay decreases (1/k)
• Wire delay not decrease, maybe increase
• Overall delay decrease less than (1/k)