Reticle Floorplanning With Guaranteed Yield for MultiProject Wafers

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Reticle Floorplanning With Guaranteed Yield for
Multi-Project Wafers
Andrew B. Kahng
Sherief Reda
ECE and CSE Dept. University of California San
Diego
CSE Dept. University of California San Diego
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• Introduction to Multi-Project Wafers
• Design Flow
• Side-to-Side Dicing Problem
• Proposed Methodology
• Floorplanning with Guaranteed Yield
• Experimental Results

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• Mask cost 1M for 90 nm technology
• Wafer cost 4K per wafer

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Image courtesy of CMP and EuroPractice

• Share rising costs of mask tooling among
  multiple prototype and low production volume
  designs ? Multi-Project Wafer

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• Introduced in late 1970s and early 1980s
• Companies MOSIS, CMP, TSMC
• Several academic approaches proposed

• Chen et al. give bottom-left fill algorithm, SPIE
  2003
• Xu, Tian, Wong and Reich, SPIE 2003
• Anderson et al. propose a grid packing algorithm,
  WADS 2003
• Kahng et al. propose dicing plans for generic
  floorplans, ISPD 2004

• Commercial Tools MaskCompose, GTMuch

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• Introduction to Multi-Project Wafers
• Design Flow
• Side-to-Side Dicing Problem
• Proposed Methodology
• Floorplanning with Guaranteed Yield
• Experimental Results

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• Unique designs

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• Custom designs
• Partition between reticles

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• Custom designs
• Partition between shuttles
• Reticle placement

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map

shot-map
print
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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design

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• Custom designs
• Partition between shuttles
• Reticle placement
• Stepper shot-map
• Dicing plan design
• Extract die

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• Introduction to Multi-Project Wafers
• Design Flow
• Side-to-Side Dicing Problem
• Proposed Methodology
• Floorplanning with Guaranteed Yield
• Experimental Results

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• Side-to-side dicing is the prevalent wafer
  dicing technology

Sliced out

• A die is sliced out if and only if
• 1. Four edges are on the cut lines
• 2. No cut lines pass through the die

Dicing is easy for standard wafers. All dice will
be sliced out.
Dicing is complex for MPW. Most dice will be
destroyed if placement is not well aligned.
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• Two dies are in conflict if they can not be
  simultaneously sliced out horizontally.
• Die 1 is in conflict with entire row of Die 2.

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dicing die 2
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dicing die 2
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dicing die 1
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dicing die 1
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reticle
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• A die copy is successfully extracted if it is
  successfully extracted in both horizontal and
  vertical dicing

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Given
A number of die designs, each with a production
volume requirement
Objective
Produce the required volumes of all dies using
the minimum amount of wafers ? maximize the
minimium amount of die copies extracted from a
wafer over all dies (Yield)
Example If die 1 has a 40 copies requirement,
and the dicing plan yields 5 valid copies per
wafer ? 8 wafers are needed
Methods

• Floorplanning the dies within the reticle
• Efficient dicing plan

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• Introduction to Multi-Project Wafers
• Design Flow
• Side-to-Side Dicing Problem and Motivation
• Proposed Methodology
• Floorplanning with Guaranteed Yield
• Experimental Results

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• Previous approaches (Kahng et al.) use regular
  area floorplanning and devise efficient dicing
  plans

Observation

• Regular area floorplanners are yield oblivious
• There is an inherent conflict between area
  minimization and yield

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Main Idea

• Construct floorplans that consider specified
  yield bounds as constraints and minimize the area

Method

• Limit floorplans to grids
• Calculate constructive lower bounds on the yield
• Specify simple rules to characterize the yield of
  a given floorplan
• Minimize the area using a branch and bround
  procedure taking the yield as a constraint

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General floorplan
Grid floorplan
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n

• Given m reticle rows and n reticle columns

reticle row

• Let ?i be the number of different height die
  copies residing in a grid row, e.g., ?12, ?11
• Let µj be the number of different width die
  copies residing in a grid column, e.g., µ11,
  µ22

grid row
m
reticle column
grid column
Lemma 1 A constructive lower bound on number of
copies that can be extracted of a die residing in
row i and column j is ?m / ? i? ? ?n / µj?
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• ?i number of different height die copies
  residing in a grid row.
• µj be the number of different width die copies
  residing in a grid column

reticle row
grid row

• Limiting the values of µj and ?i guarantees a
  lower limit on yield

reticle column
grid column
Example
Theorem 1 A lower bound on the yield is
m2-m(?i?µj)/?i?µj for a wafer with m rows and m
columns
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• Why is branch and bound feasible?
• 1. There are typically few dies per reticle
• 2. Yield constraints prune large portions of the
  search space

• branch_bound(k, yield, grid1..w1..h)
• if all dies are placed then
• evaluate the floorplan area and if area lt best
  area then area best area
• return
• expand the grid by an additional column and row
  grid1..w11..h1
• for each empty slot (i, j) in the grid
• if placing die dk in slot (i, j) does not
  violate yield constraints
• Place dk and evaluate partial area
• if partial area lt best area then
  branch_bound(k1, yield, grid1..w11..h1)
• undo placement of dk in (i, j)

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• Introduction to Multi-Project Wafers
• Design Flow
• Side-to-Side Dicing Problem and Motivation
• Proposed Methodology
• Floorplanning with Guaranteed Yield
• Experimental Results

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• Our method allows an area/yield trade off

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• Our results dominate previous approaches in both
  yield and area

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• Our results establish a Pareto frontier
  representing a trade off between area and yield

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Conclusions

• A new simple approach to reticle floorplanning
  taking yield as a constraint
• An optimal area packer using branch and bound
• Our results establish a Pareto frontier that
  trades yield for area
• Our results dominate previous approaches

Future Work

• Respecting reticle aspect ratios
• Different dicing plans for different wafers

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