CPE 431531 Chapter 6 Enhancing Performance with Pipelining - PowerPoint PPT Presentation

1 / 25
About This Presentation
Title:

CPE 431531 Chapter 6 Enhancing Performance with Pipelining

Description:

Electrical and Computer Engineering. CPE 431/531 ... Electrical and Computer Engineering. UAH. CPE 431/531. Chapter 6. 6.1 An Overview of Pipelining ... – PowerPoint PPT presentation

Number of Views:122
Avg rating:3.0/5.0
Slides: 26
Provided by: glen3
Category:

less

Transcript and Presenter's Notes

Title: CPE 431531 Chapter 6 Enhancing Performance with Pipelining


1
CPE 431/531Chapter 6 - Enhancing Performance
with Pipelining
  • Swathi T. Gurumani
  • Modified From Slides of
  • Dr. Rhonda Kay Gaede
  • UAH

2
6.1 An Overview of Pipelining -Control Hazards
Stalling
Performance of Stall on Branch Example on Pg.
380 Branch prediction Method of resolving a
branch hazard that assumes a given outcome for
the branch and proceeds from that assumption
rather than waiting to ascertain the actual
outcome Prediction to handle branches untaken,
taken
3
6.1 An Overview of Pipelining -Control Hazards
Prediction
4
6.2 A Pipelined Datapath Identifying the Stages
Control hazard
Data hazard
5
6.2 A Pipelined Datapath Representing Multiple
Instruction Execution
6
6.2 A Pipelined Datapath - Adding Pipeline
Registers
128
64
97
64
7
6.2 A Pipelined Datapath lw Instruction
Execution IF Stage
8
6.2 A Pipelined Datapath lw Instruction
Execution ID Stage
9
6.2 A Pipelined Datapath- lw Instruction
Execution EX Stage
10
6.2 A Pipelined Datapath - lw Instruction
Execution MEM Stage

11
6.2 A Pipelined Datapath - lw Instruction
Execution WB Stage

12
6.2 A Pipelined Datapath - sw Instruction
Exection EX stage
13
6.2 A Pipelined Datapath sw Instruction
Exection MEM stage
14
6.2 A Pipelined Datapath - sw Instruction
Exection WB stage
15
6.2 A Pipelined Datapath - Additions for lw and
R-type
16
6.2 A Pipelined Datapath - Datapath used by lw
17
6.2 A Pipelined Datapath - Stylized Multiple
Clock Cycle Diagrams
18
6.2 A Pipelined Datapath - Traditional Multiple
Clock Cycle Diagrams
19
6.2 A Pipelined Datapath - Single Cycle Diagram
Cycle 5 Slice
20
6.3 Pipelined Control - Identifying Control
Lines Needed
21
6.3 Pipelined Control Generating and Saving
Control Lines
  • EX - 4
  • MEM - 3
  • WB - 2

22
6.3 Pipelined Control - Putting it all Together
23
6.4 Data Hazards and Forwarding - Data
Dependencies
  • In the previous example, there were no data
    dependencies. Now, the rest of the story.
  • sub 2, 1, 3
  • and 12, 2, 5
  • or 13, 6, 2,
  • add 14, 2, 2
  • sw 15, 100(2)

24
6.4 Data Hazards and Forwarding - Which Data
Dependencies are Hazards?
  • A multiple-clock-cycle diagram is useful for
    looking at the effects of data dependencies.

25
6.4 Data Hazards and Forwarding - Classifying
Hazards
  • Type 1 The information needed in the EX stage
    by an instruction is the result of the
    instruction one stage ahead (found in the EX/MEM
    pipeline register)
  • A. The information is needed in Rrs
  • B. The information is needed as Rrt
  • Type 2 The information needed in the EX stage
    by an instruction is the result of the
    instruction two stages ahead (found in the MEM/WB
    pipeline register)
  • A. The information is needed in Rrs
  • B. The information is needed as Rrt
Write a Comment
User Comments (0)
About PowerShow.com