CPE 431531 Chapter 6 Enhancing Performance with Pipelining

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CPE 431/531Chapter 6 - Enhancing Performance
with Pipelining

• Swathi T. Gurumani
• Modified From Slides of
• Dr. Rhonda Kay Gaede
• UAH

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6.1 An Overview of Pipelining

• Pipelining is an implementation technique in
  which multiple instructions are overlapped in
  execution.
• Pipelining helps throughput, not individual
  execution time.
• It improves performance by increasing instruction
  throughput, as opposed to decreasing the
  execution time of an individual instruction.
• Instruction throughput is important because real
  programs execute billions of instructions
• You cant skip a stage when having different
  pipeline stages.

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6.1 An Overview of Pipelining -The Laundry
Analogy
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6.1 An Overview of Pipelining -MIPS Processor
Stages

• Instruction fetch (IF)
• Instruction decode and register read (ID)
• Execution (calculate address) (EX)
• Memory access (MEM)
• Register write (WB)

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6.1 An Overview of Pipelining -Single Cycle vs.
Pipelined Performance

• Consider lw, sw, add, sub, and, or, slt, beq
• Operation times memory, ALU 200 ps, register 100
  ps

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6.1 An Overview of Pipelining -Single Cycle vs.
Pipelined Timeline

• The pipeline stage times are limited by the
  slowest resource

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6.1 An Overview of Pipelining -Designing
Instruction Sets for Pipelining

• All MIPS instructions are the same length
• (32 bits).
• Easier to fetch and decode
• MIPS has only a few instruction formats.
• Source register fields located in the same place
• Memory operands appear only in loads or stores.
• Use the execute stage to calculate address
• Operands must be aligned in memory.

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6.1 An Overview of Pipelining -Pipeline Hazards

• Hazard Next instruction cannot execute in the
  next clock cycle
• Structural Hazard - not enough hardware
• Not having two memories
• Data Hazards one instruction needs the result
  of another
• Control Hazard (branch hazard) - decisions arent
  made
• Conservative Approach stall
• Alternative Approach predict

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6.1 An Overview of Pipelining- Data Hazards

• A data hazard occurs when a needed result has not
  yet been written to the register file.
• Consider
• add s0, t0, t1
• sub t2, s0, t3
• Though the result is not written until WB, it is
  available after the add has finished the EX
  stage, forward it to the right place.

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6.1 An Overview of Pipelining -Data Hazards Two
Instruction Forwarding

• Forwarding paths are valid only if the
  destination stage is later in time than the
  source stage.

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6.1 An Overview of Pipelining -Data Hazards
More on Forwarding

• Forwarding cant fix everything.
• Consider
• lw s0, 20(t1)
• sub t2, s0, t3

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6.1 An Overview of Pipelining -Data Hazards
More on Forwarding

• Load-use data hazard Data hazard in which data
  requested by a load instruction has not yet
  become available when it is requested
• Pipeline stall stall initiated in order to
  resolve a hazard
• Also called bubble

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6.1 An Overview of Pipelining -Data Hazards The
Compiler Can Help

• Consider the following
• A B E
• C B F
• lw t1, 0(t0)
• lw t2, 4(t0)
• add t3, t1, t2
• sw t3, 12(t0)
• lw t4, 8(t0)
• add t5, t1, t4
• sw t5, 16(t0)

lw t1, 0(t0) lw t2, 4(t0) lw t4,
8(t0) add t3, t1, t2 sw t3,
12(t0) add t5, t1, t4 sw t5, 16(t0)
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6.1 An Overview of Pipelining -Control Hazards
Stalling
Performance of Stall on Branch Example on Pg.
380 Branch prediction Method of resolving a
branch hazard that assumes a given outcome for
the branch and proceeds from that assumption
rather than waiting to ascertain the actual
outcome Prediction to handle branches untaken,
taken
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6.1 An Overview of Pipelining -Control Hazards
Prediction