Topic 6: Pipelining and Pipelined Architecture

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Topic 6Pipelining and Pipelined Architecture
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Reading List

• Slides Topic6x
• Henn Patt Chapter 6
• Other papers as assigned in class or homeworks

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Pipelining

• What is pipelining - basic concepts
• Pipelined datapath A case study of MIPS
• Pipeline control
• Pipeline hazard resolution

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• Pipelining
• the basic concepts

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Basic Concept

• Pipeline multiple instructions are
  simultaneously in execution
• Pipeline is divided into segments or stages
• Machine cycle
• Time required to move through one stage
• Machine cycle is determined by the slowest stage
  in the pipe
• Often

Machine Clock cycle cycle
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• In a perfectly balanced pipelined machine
  instruction time
• In a normal machine
• (1) is not true,
• i.e. - stage time does not equal there is
• overhead
• but it can be very close to 10 within (1)

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Pipelining as an Architecture Technique

• Generally may be invisible to user
• Scalar pipelined machine vs. vector machine

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• Pipeline throughout
• So pipeline increases throughout, but the time
  for execution of each instruction remains
  unchanged.
• Clock rate of a pipelined machine is limited by
• latch time
• clock skew
• the delay time required for clock signals to
  propagate on a chip.

of instructions completed
cycle
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Performance Limitations of a Pipeline

• Rate cannot exceed the slowest stage
• Complexities in reality
• - different processing time for different stages
• - interaction/dependencies between stages - may
  be data dependent (dynamic)

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(b)
The most important factors on pipe beat (cycle
time) latch delay and clock skew
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Overlap vs. Pipeline

• Pipeline
• tightly coupled subfunctions
• fixed basic stage time
• independent basic function evaluation
• Overlap
• Loosely coupled subfunctions
• variable basic stage time
• dependency between function evaluation

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1 Task 1 Task 2 Task 1
Task 3 . . . 2 Task 2 Task 1
Task 3 Task 1
Time Idle time
CPU/I/O Overlapping
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MIPS Pipeline

• Pipeline stages
• IF
• ID (decode Reg fetch)
• EX
• MEM
• Write back

On each clock cycle another instruction is
fetched and begins its five-step execution. If an
instruction is started every clock cycle, the
performance will be five times that of a machine
that is not pipelined.
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MIPS Pipeline - Another Representation