RPC Electronics Status

1
RPC Electronics Status

• Overall system
• TDC
• Digitizing frequency issue
• (determine the bin size of the TDC value)
• Discriminator test result
• Trigger module status
• Fabrication

2
On chamber
TDC
Disc.
Altera Cyclone II FPGA
16 channels cable input
32 channel
16 channels cable input
Serial download
20X4rows connectors
32 bits L1 trigger
(Timing bin 106ns/64)
Data
Disc.
Altera Cyclone II FPGA
16 channels cable input
32 channel
16 channels cable input
Serial download

RPC(HBD) crate/BUS structure 6Ux160 mm VME size
Output To DCM
T D C
T D C
Output To L1
Clock fanout
Clock Master
8/6 TDCs
Slow Control
GTM
DCM
L1 primitives
L1
3
RPC Discriminator board
CMS RPC discriminator chip
Temporary programming jig
power
LVDS discriminator output
Signal flow
RPC TDC board
L1 data
DCM data
Cable adapter board
4
TDC digitizing frequency issue

• The FPGA uses 4x beam clock to generating the
  digitizing frequency. This frequency drive a
  counter. Discriminator pulse stop the counter. gt
  TDC value
• Original idea is have use both edges of 320 MHz,
  840 MHz, as TDC counter clock. One set per
  channel. 32 channel per chip
• The circuit associate with positive and negative
  edges of the clock are routed as independent
  circuits.
• The circuits associate with the positive and
  negative clock edges has slightly different delay
  than ½ clock cycle.
• The two counters need to be aligned within 1.65ns
  to be useful. Otherwise one can not aligned the
  counters between positive and negative edge.
• As an backup solution, we use 44 beam clock
  frequency as the clock for TDC counter, 2.5ns
  time bin with 9.6MHz RHIC clock.
• This is still better than we claim in the CDR,
  i.e. 3.3ns.
• In the mean time, we will still try to improve
  the 320 MHz compiling result.

5
The TDC Internal Test Pulse Scan
average TDC value
Sigma on the TDC
test pulse step
test pulse step
6
Discriminator test

• One can inject test pulse into the CMS
  discriminator chip.
• The test pulse couple into the input through
  1.2pf capacitor. The negative edge of the pulse
  need to come first.
• This can be used to verify the cable or channel
  alive test. It is not mean to be used as
  calibration of the discriminator chips.
• One can also inject pulse into the front end.
• Threshold effect study.
• Input pulse height scan. (to be done)
• Test run for the Old and new chips .
• Check for the 10m cables drives

7
Test pulse setting 0xc0 8mv input 8 mv per
step. Old chip
Channel 26
Channel 26
Channel 32
Channel 32
8
Test pulse setting 0x60 4mv input 8 mv per
step. (old chip)
CMS Disc threshold
Channel 26
Channel 26
Channel 28
TDC
Channel 32
Channel 30
Channel 32
Threshold (8 mv per step)
TDC distribution at step 20 (160mv)
9
Test pulse setting 0x40 2.7 mv input 8 mv per
step. (old chip)
Channel 26
Channel 26
Channel 28
Channel 30
Channel 32
Channel 32
10
Test pulse setting 0x60 4mv input 8 mv per
step. New chip ground tight
Channel 26
Channel 26
Channel 28
Channel 32
11
Test pulse setting 0x60 4mv input 8 mv per
step. New chip ground disconnected.
12
Discriminator Test pulse input vs. discriminator
threshold. 4 mv per step. Old board
Channel 12 TDC distribution, DAC step 80
TDC
step
13
Test pulse input vs. discriminator threshold. 4
mv per step. New chip, Analog/digital ground
separated.
Channel 14 TDC distribution, DAC step 80
TDC
step
14
Test pulse input vs. discriminator threshold. 4
mv per step. New chip, DC/AC ground jumper
connected
Channel 14 TDC distribution, DAC step 80
Chnl14
TDC
step
15
DISC LVDS output at discriminator board
1.4V
DISC output after 10 meter cables
1.63V
69 ns time difference 1.61ns/ft ? 42 ft
Digitally subtracted pulse between and side
of discriminator LVDS output 500mv per division
16
Trigger Module

• We have start to work on the trigger module FPGA
  code.
• We will start with the design base on the the
  possibility the strips will be connected at the
  detector, i.e. the FEM will output 64 trigger
  bits per beam clock.
• There is no TDC module changes to accommodate
  this changes.
• It will take us probably till late August/early
  September to finish all the coding and layout the
  board.
• There is no budget to fabricate this board.
• Fund are re-allocated to the purchase of the
  parts for the factory setup and coming run.

17
Fabrication Status

• We are starting to assemble the discriminator
  modules in house with the final cable connectors,
  gt12 finished.
• We have the clock master, clock fanout, TDC
  boards and parts.
• Waiting for the purchase order for the assembly.
• For backplane, we are waiting for the purchase
  order for the boards.
• We need to work on the data taking software