10Nov05

1
Electronics Issues, Frontend (Strips that is, not
Pixels) US-ATLAS Upgrade RD Meeting UCSC 10-Nov-
2005 A.A. Grillo SCIPP UCSC
2
Experience

• We have shown for past experiments that the
  bipolar technology has advantages over CMOS in
  power and performance for front-end amplification
  of silicon strip readout when the capacitive
  loads are high and the shaping times short.
• ZEUS-LPS Tek-Z IC
• SSC-SDC LBIC IC
• ATLAS-SCT ABCD, CAFE-M, CAFE-P ICs
• CMOS is the preferred technology for back-end
  data processing but biCMOS technologies have not
  been readily available, making it difficult to
  find a one chip solution.
• Experience with the commercial 0.25 mm CMOS has
  shown the great advantage of using a high volume
  commercial rather than a niche technology.

3
Technical Issues

• The ATLAS-ID upgrade will put even larger
  constraints on power.
• Can we meet power and shaping time requirements
  with deep sub-micron CMOS?
• Achieving sufficient transconductance of the
  frontend transistor typically requires large bias
  currents.
• The changes that make SiGe Bipolar technology
  operate at 100 GHz for the wireless industry
  coincide with the features that enhance
  performance for our application.
• Small feature size increases radiation tolerance
• Extremely small base resistance (of order 10-100
  W) affords low noise designs at very low bias
  currents.
• Can these features help us save power?
• Will the SiGe technologies meet rad-hard
  requirements?

4
Example CMOS Front-End
J. Kaplon et al., 2004 IEEE Rome Oct 2004, use
0.25 mm CMOS
Can SiGe beatthese numbers?
For CMOS Input transistor 300 mA, other
transistors 330 mA (each 20 90 mA)
5
biCMOS with Enhanced SiGe

• The market for wireless communication has now
  spawned many biCMOS technologies where the
  bipolar devices have been enhanced with a
  germanium doped base region (SiGe devices).
• We have identified at least the following
  vendors
• IBM (at least 3 generations available)
• STm
• IHP, (Frankfurt on Oder, Germany)
• Motorola
• JAZZ
• Advanced versions include CMOS with feature sizes
  of 0.25 mm to 0.13 mm.
• The bipolar devices have DC current gains (b) of
  several 100 and fTs up to 200s of GHz. This
  implies very small geometries that could afford
  higher current densities and more rad-hardness.

Growing number of fab facilities
6
Radiation vs. Radius in Upgraded Tracker
The usefulness of a SiGe bipolar front-end
circuit will depend upon its radiation hardness
for the various regions (i.e. radii) where
silicon strip detectors might be used.
7
Tracker Regions Amenable for SiGe
For the inner tracker layers, pixel detectors
will be needed, and their small capacitances
allow the use of deep sub-micron CMOS as an
efficient readout technology. Starting at a
radius of about 20 cm, at fluence levels of 1015
n/cm2, short strips can be used, with a detector
length of about 3 cm and capacitances of the
order of 5 pF. At a radius of about 60 cm, the
expected fluence is a few times 1014 p/cm2, and
longer strips of about 10 cm and capacitance of
15 pF can be used. It is in these two outer
regions with sensors with larger capacitive loads
where bipolar SiGe might be used in the front-end
readout ASICs with welcome power savings while
still maintaining fast shaping times.
8
Biasing the Analogue Circuit
The analog section of a readout IC for silicon
strips typically has a special front transistor,
selected to minimize noise (often requiring a
larger current than the other transistors), and a
large number of additional transistors used in
the shaping sections and for signal-level
discrimination. The current for the front
transistor is selected in order to achieve the
desired transconductance (minimize noise). For
the other bipolar devices, bias levels for the
other transistors are determined to achieve the
necessary rad-hardness, matching and shaping
times. Depending upon the performance
(especially radiation hardness) of the bipolar
process, power savings could be realized in both
the front transistor and in the other parts of
the analogue circuit.
9
Evaluation of SiGe Radiation Hardness
The Team D.E. Dorfan, A. A. Grillo, J. Metcalfe,
M Rogers, H. F.-W. Sadrozinski, A. Seiden, E. N.
Spencer, M. Wilder SCIPP-UCSC Collaborators A.
Sutton, J.D. Cressler Georgia Tech, Atlanta, GA
30332-0250, USA M. Ullan, M. Lozano CNM,
Barcelona and newly joined S. Rescia et al.BNL
10
First SiGe High-rate Radiation Testing
Radiation testing has been performed on some SiGe
devices by our Georgia Tech collaborators up to a
fluence of 1x1014 p/cm2 and they have
demonstrated acceptable performance. (See for
example http//isde.vanderbilt.edu/Content/muri/2
005MURI/Cressler_MURI.ppt) In order to extend
this data to higher fluences, we obtained some
arrays of test structures from our collaborator
at Georgia Tech. These were from a b-enhanced
5HP process from IBM. (i.e. the b was 250
rather than 100.) The parts were tested at UCSC
and with the help of RD50 collaborators (Michael
Moll Maurice Glaser) they were irradiated in
Fall 2004 at the CERN PS and then re-tested at
UCSC. For expediency, all terminals were grounded
during the irradiation This gives slightly
amplified rad effects than with normal biasing.
Annealing was performed after initial post-rad
testing.
11
Irradiated Samples
12
Radiation Damage Mechanism
Forward Gummel Plot for 0.5x2.5 mm2 Ic,Ib vs.
Vbe Pre-rad and After 1x1015 p/cm2 Anneal Steps
Collector current remains the same
Ic , Ib A
Base current increases after irradiation
Vbe V

• Ionization Damage (in the spacer oxide layers)
• The charged nature of the particle creates oxide
  trapped charges and interface states in the
  emitter-base spacer increasing the base current.
• Displacement Damage (in the oxide and bulk)
• The incident mass of the particle knocks out
  atoms in the lattice structure shortening hole
  lifetime, which is inversely proportional to the
  base current.

13
Annealing Effects
Before Irradiation
After Irradiation
After Irradiation Full Annealing
We studied the effects of annealing. The
performance improves appreciably. In the case
above, the gain is now over 50 at 10mA entering
into the region where an efficient chip design
may be implemented with this technology. The
annealing effects are expected to be sensitive to
the biasing conditions. We plan to study this in
the future.
14
Initial Results
Before Irradiation
Increasing Fluence
Lowest Fluence
Current Gain, b
Highest Fluence
After irradiation, the gain decreases as the
fluence level increases. Performance is still
very good at a fluence level of 1x1015 p/cm2. A
typical Ic for transistor operation might be
around 10 mA where a b of around 50 is required
for a chip design. At 3x1015, operation is still
acceptable for certain applications.
15
Universality of Results
D(1/b) Post-rad Anneal to Pre-rad _at_ Jc10mA
Ratio of Current Gain, b Post-rad Anneal to
Pre-rad _at_ Jc10 mA
1/b(final) - 1/b(initial)
Ratio b(final)/b(initial)
Proton Fluence p/cm2
Proton Fluence p/cm2
Universal behavior independent of transistor
geometry when compared at the same current
density Jc. For a given current density D(1/b)
scales linearly with the log of the fluence. This
precise relation allows the gain after
irradiation to be predicted for other SiGe HBTs.
Note there is little dependence on the initial
gain value.
16
Feasibility for ATLAS ID Upgrade
Qualifications for a good transistor A gain of
50 is a good figure of merit for a transistor to
use in a front-end circuit design. Low currents
translate into increased power savings.
At 1.34x1015 closer to the mid radius (20 cm),
where short (3 cm) silicon strip detectors with
capacitance around 5pF will be used, the
collector current Ic is still good for a front
transistor, which requires a larger current while
minimizing noise. We expect better results from
3rd generation IBM SiGe HBTs.
At 3.5x1014 in the outer region (60 cm), where
long (10 cm) silicon strip detectors with
capacitances around 15pF will be used, the
collector current Ic is low enough for
substantial power savings over CMOS!
17
IHP Design to Estimate Power of Upgrade Frontend

• IHP has the SG25H1 200 GHz SiGe process available
  on Europractice. b is 200. In parallel with
  radiation testing by Barcelona, UCSC is
  developing an eight channel amplifier/comparator
  with similar specifications to the present ABCD.
• The x4 minimum transistor has base resistance of
  51 W, 0.21 mm x 3.36 mm. 0.25 mm CMOS is also
  included. Extensive use is made of the 2.0 kW/
  square unsilicided polysilicon resistor
  structure, since this is expected to be radiation
  resistant.
• The purpose of this FE design is to estimate the
  low current bias performance of SiGe, and to see
  whether it can produce significant power savings.
  The target voltage bias level is 2 V.

18
Design Procedure Details

• IHP provides a Cadence Kit, with support for both
  Diva and Allegro.
• The bipolar devices are complete as provided, no
  editing allowed, with some hidden layers to
  protect IHP intellectual property.
• Radiation hard annular NMOS transistor drawing is
  well supported. This is done by allowing 135
  degree bends of Poly lines on Active in the DRC.
  There are included Virtuoso utilities that are
  needed for successful DRC.
• Cadence Spectre does not DC converge well.
  Mentor has Eldo utility Artist Link that
  enables Eldo to run with Cadence schematic
  Composer. Eldo converges vigorously. Overall,
  the Cadence Kit is complete enough, and with the
  help of Eldo, is a good toolset.

19
Frontend Simulation Results
20
First Guess at Potential Power Savings
Using similar estimates of bias settings and
transistor counts, an estimate for power can be
obtained.
1.1 mW
0.16mW
Total Power (25 pF) 3x1014
1.5 mW
21
Conclusions on SiGe Evaluation So Far
First tests of one SiGe biCMOS process indicate
that the bipolar devices may be sufficiently
rad-hard for the upgraded ATLAS tracker,
certainly in the outer-radius region and even
perhaps in the mid-radius region. A simulation
estimate of power consumption for such a SiGe
front-end circuit indicates that significant
power savings might be achieved. More work is
needed to both confirm the radiation hardness and
arrive at more accurate estimates of power
savings. In particular, with so many potential
commercial vendors available, it is important to
understand if the post-radiation performance is
generic to the SiGe technology or if it is
specific to some versions.
22
Work Ahead

• Along with our collaborators, we plan two
  parallel paths of work.
• First, we plan more irradiations with several
  SiGe processes. In particular, we plan to test
  at least the IBM 5HP, IBM enhanced 5HP, IBM 8HP,
  IHP SG25H1 and one from STm.
• CNM has obtained a first set of test structures
  from IHP and is proceeding.
• UCSC has recently received the IBM test
  structures.
• We have been promised test structures from STm
  but a schedule is not yet fixed.
• Irradiations will be done with neutrons
  (Ljubljana), gammas (BNL) and protons (CERN).
• To obtain a better handle on the true power
  savings, we will submit an IHP 8 channel
  amplifier/comparator early in 2006. This work is
  in parallel with IHP radiation characterization.

23
Other Issues

• Joining forces with CMOS
• As was pointed out, the data processing backend
  of the readout IC will use CMOS technology.
• The SiGe technologies we are looking at come with
  0.25 mm to 0.13 mm CMOS, so a biCMOS solution is
  possible.
• It is assumed that these CMOS technologies will
  be or can be made rad-hard as the 0.25 mm process
  was for current ATLAS. However, this required
  2-3 man-years to modify the IBM standard cell
  library.
• The current CERN-IBM frame contract will expire
  at end of 2006.
• The tendering process for a new frame contract
  has started and SiGe is stated as an option, but
  only an option.

24
More Issues

• Joining forces with CMOS (cont.)
• If a frame contract is signed for a technology
  that does not include SiGe, the SiGe biCMOS may
  require a duplication effort for library
  conversion.
• A new frame contract itself may be an issue since
  the total number of wafers expected for LHC
  Upgrade is expected to be much less than it was
  for the present LHC construction and IBM has
  already expressed disappointment in volume.
• With or without a frame contract, it would be
  very unfortunate (and possibly not financially
  viable) to be forced to modify two CMOS
  libraries, one for straight CMOS (e.g. for
  Pixels) and one for SiGe biCMOS.

25
Yet More Issues

• Readout architecture
• The present readout IC uses binary readout
  (hit/no-hit).
• There is not universal satisfaction with this
  within the present SCT community
• There is a call to re-evaluate the architecture
  choice
• Choice will be driven by lowest power option
• There is a proposal to build an ABCD-next IC on
  0.25 mm CMOS
• Prototype vehicle for detector development
• Dual polarity input
• Compatible with present SCT DAQ
• Some power regulation structures
• No identified funding source as yet