Study Guide for Exam 2

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Study Guide for Exam 2
2
Memory Organization

• Memory is constructed of RAM chips, often
  referred to in terms of length ? width.
• If the memory word size of the machine is 16
  bits, then a 4M ? 16 RAM chip gives us 4
  megabytes of 16-bit memory locations.
• We observe that 4M can be expressed as 2 2 ? 2 20
  2 22 words.
• The memory locations for this memory are numbered
  0 through 2 22 -1.
• Thus, the memory bus of this system requires at
  least 22 address lines.

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High-order Interleaving
4
Low-order Interleaving
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MARIE

• 4K words of word-addressable main memory.
• 16-bit data words.
• 16-bit instructions, 4 for the opcode and 12 for
  the address.
• A 16-bit arithmetic logic unit (ALU).
• Seven registers for control and data movement.

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MARIEs seven registers

• Accumulator, AC, a 16-bit register that holds a
  conditional operator (e.g., "less than") or one
  operand of a two-operand instruction.
• Memory address register, MAR, a 12-bit register
  that holds the memory address of an instruction
  or the operand of an instruction.
• Memory buffer register, MBR, a 16-bit register
  that holds the data after its retrieval from, or
  before its placement in memory.
• Program counter, PC, a 12-bit register that holds
  the address of the next program instruction to be
  executed.
• Instruction register, IR, which holds an
  instruction immediately preceding its execution.
• Input register, InREG, an 8-bit register that
  holds data read from an input device.
• Output register, OutREG, an 8-bit register, that
  holds data that is ready for the output device.

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MARIE architecture and data path
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MARIEs instruction format
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Microoperations and register transfer language
(RTL).

• The RTL for the LOAD instruction is
• Similarly, the RTL for the ADD instruction is

MAR ? X MBR ? MMAR AC ? MBR
MAR ? X MBR ? MMAR AC ? AC MBR
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Sample Program Translate to C

• 100 LOAD Addr
• 101 STORE Next
• 102 LOAD Num
• 103 SUBT One
• 104 STORE Ctr
• 105 Loop LOAD Sum
• 106 ADDI Next
• 107 STORE Sum
• 108 LOAD Next
• 109 ADD One
• 10A STORE Next
• 10B LOAD Ctr
• 10C SUBT One
• 10D STORE Ctr

10E SKIPCOND 000 10F JUMP Loop 110
HALT 111 Addr HEX 118 112 Next HEX 0 113
Num DEC 5 114 Sum DEC 0 115 Ctr HEX
0 116 One DEC 1 117 DEC 10 118 DEC
15 119 DEC 2 11A DEC 25 11B DEC 30
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Instruction Formats

• In a one-address ISA, like MARIE, the infix
  expression,
• Z X ? Y W ? U
• looks like this
• LOAD X
• MULT Y
• STORE TEMP
• LOAD W
• MULT U
• ADD TEMP
• STORE Z

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Instruction Formats

• In a two-address ISA, (e.g.,Intel, Motorola), the
  infix expression,
• Z X ? Y W ? U
• might look like this
• LOAD R1,X
• MULT R1,Y
• LOAD R2,W
• MULT R2,U
• ADD R1,R2
• STORE Z,R1

Note Two-address ISAs usually require one
operand to be a register.
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Instruction Formats

• With a three-address ISA, (e.g.,mainframes), the
  infix expression,
• Z X ? Y W ? U
• might look like this
• MULT R1,X,Y
• MULT R2,W,U
• ADD Z,R1,R2

Would this program execute faster than the
corresponding (longer) program that we saw in the
stack-based ISA?
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Instruction Formats

• A system has 16 registers and 4K of memory.
• We need 4 bits to access one of the registers. We
  also need 12 bits for a memory address.
• If the system is to have 16-bit instructions, we
  have two choices for our instructions

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Instruction Formats

• If we allow the length of the opcode to vary, we
  could create a very rich instruction set

Is there something missing from this instruction
set?
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Addressing

• These are the values loaded into the accumulator
  for each addressing mode.

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Virtual Memory

• Information concerning the location of each page,
  whether on disk or in memory, is maintained in a
  data structure called a page table (shown below).
• There is one page table for each active process.