Microprocessor Optimizations for Network Protocol Implementation

1
Microprocessor Optimizations for Network Protocol
Implementation

• Kevin Camera, Tim Tuan
• CS252 Fall 1999

2
Overview

• Motivation
• The problem, the needs, our approach
• Methodology
• Analysis of wireless protocol on a configurable
  processor
• Intercom protocol Xtensa platform
• Results
• Optimizations
• Performance gain
• Conclusion

3
Motivation

• Problem
• How to implement protocols efficiently?
• Where is the need? In a more ubiquitous computing
  environment
• Need low-cost, low-power devices with high
  network performance
• Wireless communication
• Our Approach
• Look for optimizations in microprocessor
  implementation

4
Intercom

• A set of wireless protocols (BWRC)
• Designed for multinode, wireless intercom systems
• We examine the control layer
• Time-division multiple access (TDMA) control
• Channel usage management
• Designed with Telelogic Tau

Control
Currently in ARM
MAC
Link
Currently in Xilinx
Physical
Figure 1. Intercom protocol stack, and the
current implementation platforms.
5
Xtensa Processor

• Highly configurable core
• Base processor matched to SA-1100
• Extensible instruction set via TIE
• Generates custom SW toolkit
• Unfortunate shortcomings
• No cache associativity
• No branch or memory extensibility

The Xtensa Processor Generator is a product of
Tensilica, Inc.
6
OptimizationMemory Routines

• Problem
• CPU time 32 calloc, 11 memcpy
• Cause
• Protocol runs on Telelogic Cmicro kernel
• Solutions
• Indirect load table
• Non-blocking data cache

7
Optimization Branches

• Problems
• 31 more branches taken than not-taken
• Xtensa does not have branch prediction (NT)
• Same applies for ARM
• Cause
• Maintaining slot set database requires loops
• Solutions
• A simple branch prediction scheme would improve
  performance 12
• Reduce power by increasing branch stall penalty

8
OptimizationProcedure Calls

• Problem
• 14.7 of all instructions are for calls!
• Cause
• Tool-generated source code excessively modular
• Solutions
• Overlapped load / procedure call
• Larger physical register file

9
Future Work

• Compile our own memory routines
• Use TIE and Xtensa runtime simulator to verify
  our improvements
• Investigate alternatives to typical kernel memory
  management
• Target power reduction

10
Conclusions

• Devices on wireless networks need an efficient
  protocol implementation
• Upper layer of protocol is dominated by processor
  control flow
• Artifacts of the design tools are significant and
  unavoidable