Requirements for Models of Achievable Routing

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Requirements for Models ofAchievable Routing

• Andrew B. Kahng, UCLA
• Stefanus Mantik, UCLA
• Dirk Stroobandt, Ghent Univ.
• Supported by Cadence Design Systems, Inc. and
• the MARCO Gigascale Silicon Research Center

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Outline

• Models of achievable routing
• Review of existing models
• Validation of models through experiments!
• Experimental analysis of assumptions
• Future model requirements
• Conclusions

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Models of achievable routing

• wirelength estimation models (Donath, )
• actual placement information

• Required versus available resources

• Required versus available resources

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Models of achievable routing

• Required versus available resources

• limited by routing efficiency factor hr

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Models of achievable routing

• Required versus available resources

• limited by power/ground (signal net fraction si)

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Models of achievable routing

• Required versus available resources

• limited by via impact factor vi (ripple effect)
• utilization factor Ui (available / supplied area)

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Use of achievable routing models

• Optimizing interconnect process parameters for
  future designs (number of layers, wire width and
  pitch per layer, ...)
• With given layer characteristics predict the
  number of layers needed
• If number of layers fixed oracle (not)
  routable!
• (SUSPENS, GENESYS, RIPE, BACPAC, GTX)
• Supplying objectives that guide layout tools to
  promising solutions (wire planning)

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Validation is key

• Models must be accurate, must support empirical
  verification and calibration
• No existing model is validated with real
  place-and-route data
• Our work concentrates on validation
• understanding reasons for validation gap
• processes for model validation
• improvements needed in future models

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Review of existing models

• Sai-Halasz Proc. IEEE, 1995
• power/ground si 20
• routing efficiency hr 40
• via impact each layer blocks 15 on layers below
  with same pitch
• model is widely used
• model is rather pessimistic

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Review of existing models (cont.)

• Chong and Brayton SLIP, 1999
• layer assignment model
• layer pairs form tiers (H and V)
• wires are routed on 1 tier
• shorter wires on lower tiers
• available resources model
• constant routing efficiency for all layers hr
  65
• via impact factor vi based on actual via area
• each wire uses 2 via stacks (block wires on lower
  layers)
• total number of wires per layer (thus vias)
  defined by layer assignment model

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Review of existing models (cont.)

• Chen et al. private communication, 1999
• layer assignment model similar to Chongs
• available resources model
• constant routing efficiency (40 lt hr lt 66)
• via impact model
• terminal vias and turn vias
• each wire uses 2 via stacks
• number of terminal vias defined
• by layer assignment model
• sparse via model Chong
• dense via model give up 1 track every X tracks
• results in via impact proportional to
  sqrt(Chongs impact factor)

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Model validation

• Models can be validated only by testing against
  comparable experimental results
• none of reviewed models was validated
• even simple comparison huge differences

Utilization factor/layer ()
0
1
3
4
5
Via fill rate ()
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Model validation (cont.)

• Experimental validation
• Typical industry standard-cell block design
• 42.000 cells, 1999, 5 layers
• Cadence placement and gridded routing tools
• same pitch (1 mm) for all layers
• via size .62 mm
• all pins for cells are on M1

• Experimental validation
• ensure congested design

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Model validation (cont.)

• Experimental validation
• adding virtual vias on M3 and M4 (effect of wires
  on virtual upper layers)

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Model validation (cont.)

• Predictions for future designs
• number of layers gtgt, die size lt f gtgtgt
• via impact severely underestimated
• predicted limits on number of layers too high

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Model validation (cont.)

• Predictions for future designs

Number of terminal vias
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Outline

• Models of achievable routing
• Review of existing models
• Validation of models through experiments!
• Experimental analysis of assumptions
• Future model requirements
• Conclusions

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Routing efficiency

• Constant over all layers?

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Routing efficiency

• Are we measuring routing efficiency or
  inefficiency?
• thought experiment
• given placement of given netlist
• route with very good router, measure Ui
• route again with very bad router, measure Ui
• which one has better routing efficiency?
• which one has higher utilization factor?
• Give credit for completing nets, not for using
  metal (use Steiner length instead of actual
  length for Ui)!

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Layer assignment assumptions

• shorter wires on lower tiers / wires on 1 tier

Actual Length ()
Actual Number of Layers
Steiner Length (?m)
Steiner Length (?m)
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Real Wiring Effects

• Cascade/ripple effect
• Effect of vias depends on wire length
• Proposal

l1 intersections
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Real Wiring Effects (cont.)

• A simple proposal
• probability wire is not blocked
• via impact factor

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Conclusion

• Better/more accurate models needed
• understanding routing efficiency
• layer assignment model allows gt1 tier/wire
• via impact based on real wiring effects
• wirelength on layer is important
• cascade/ripple effect
• Experimental verification of models a must!
• There is a lot of work yet to be done

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Constant via impact factor

• Utilization factor constant?

M3/M4 Utilization factor ratio
Via fill rate ()