TOF Electronics Overview

1
TOF Electronics Overview

• J. Schambach
• University of Texas
• STAR Review, BNL, 26 Jan 2006

2
Outline

• Electronics Essential Model
• Current (Run 5 6) System Status
• Requirements Performance
• Low Voltage System
• Production Testing
• Crosstalk, Cosmics Testing
• Electronics Installation

3
TOF Electronics Top Level
4
Electronics for One Side
5
Tray Level Electronics
6
Front-End Electronics TINO
8 per tray 960 total
7
ALICE NINO Chip
8
MRPC Digitizer TDIG
8 per tray 3 per start side 966 total
9
HPTDC Time Measurement
HPTDC is fed by a 40 MHz clock giving us a basic
25 ns period (coarse count). A PLL (Phase Locked
Loop) device inside the chip does clock
multiplication by a factor 8 (3 bits) to 320 MHz
(3.125 ns period) . A DLL (Delay Locked Loop)
done by 32 cells fed by the PLL clock acts as a
5 bit hit register for each PLL clock (98 ps
width LSB 3.125 ns/32). 4 R-C delay lines
divide each DLL bin in 4 parts (R-C
interpolation)
10
HPTDC Buffering Readout
8 channel _at_ 25ps or 32 channels _at_ 100ps
Level-0 Trigger
Bunch Crossing Hit Buffer
Level-0 Buffering
11
INL Correction

• Sigma 0.9 timebins 22 ps
• Implies single channel resolution of 16ps

12
Tray Controller TCPU
1 per tray 1 per Start Detector 122 total
13
DAQ/Trigger Interface THUB
2 per Detector side 4 total
14
THUB Design
15
ALICE DDL Link
Front-end electronics
DDL SIU
Detector Data Link
Optical Fibre 200 meters
DDL DIU
RORC
Read Out Receiver Card
PC
Data Acquisition PC
16
PMT Input Board TPMT
3 per Start Detector 6 total
17
Interface to L0 trigger

• Provides multiplicity at 9.4 MHz with lt700 ns
  latency.
• The multiplicity range is 0-24 for each tray,
  where a bit is added to the sum if any of the 8
  TOF channels in a NINO chip is above threshold.
• The multiplicity sum is formed asynchronously and
  sent to L0 where it is gated and readout by the
  DSMI.
• The RHIC clock is not used anywhere by the TOF
  electronics (other than to strobe in trigger
  commands).

18
Interface to L2 trigger

• TOF will provide a 23K bit map of the TOF hits to
  L2 for each L0 accept command
• STAR L2 Trigger could use the CERN/ALICE DDL link
  that will also be the fiber interface between all
  STAR detector subsystems and DAQ in the upgraded
  STAR detector to receive L2 trigger data from
  detector subsystems.
• Alternatively, TOF could put the transmitter
  parts of the STP interface on THUB to provide
  these data.
• STAR should consider the TOF-L2 connection as a
  model for the future connection of EMC and
  additional subsystems to L2

19
Current System Status
20
Essential Model
21
Run 5/6 Setup
22
Run 5/6 Setup
23
Run 5/6 Setup
24
Run 5/6 Setup
25
Run 5/6 Setup
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Remaining Development Work

• TINO to replace TAMP
• TPMT with Discriminators
• TDIG with 3 TDCs each measuring leading and
  trailing edge times
• THUB
• Level-0 Multiplicities
• Level-2 bitmap (firmware only)
• Level-2 event buffering

27
TINO RD

• Motivation Replace Maxim Amplifier Comparator
  of TAMP with custom ASIC NINO
• Cost
• Power (no negative supply lower power)
• Fully differential better match to HPTDC
• Pulse stretching one TDC can measure both
  leading trailing edge
• Prototype designed and successfully built _at_ Rice
• Automated TINO production has been achieved
• Cosmic ray testing currently ongoing _at_ UT
• Preliminary results timing resolution similar to
  TAMP

28
Rework of TDIG

• Eliminate comparators
• Eliminate negative voltage
• Eliminate 1 TDC, other 3 TDCs measuring leading
  trailing edges
• Add Level-0 Multiplicity logic
• Add power sequencing, solid reset on power-up
• Add remote configuration of logic devices
• Change interconnect cable size and layout
• Adapt physical dimensions to new tray layout

29
THUB RD

• Needed to concentrate data before sending to DAQ
  in order to reduce the number of DAQ-fiber
  interfaces
• Prototype currently in design stage _at_ UT
• TCPU-THUB interfaces as daughter cards to
  investigate different options
• I/F as (cheap) SERDES with (cheap) CAT-5/6 cables
• Clock recovery from SERDES or separate
  (differential) Coax?
• Lots of functionality already tested with current
  TCPU in Run 5

30
Board Status
31
Requirements Performance
32
Expected Performance
33
DAQ Data Rates
34
Interface to DAQ

• The TOF system needs to be faster than the
  upgraded TPC so as not to introduce any
  additional dead time. The TOF information is only
  useful in a STAR event if the TPC is also readout
  in that event.
• The system will handle L0 accept commands at gt10
  kHz.
• The system will handle L2 accept commands at gt2
  kHz
• A design issue with some expense consequence is
  the required size of the pre-L2 buffer. How many
  tokens will be allowed in the system for events
  with TPC/TOF readout? TOF is planning to allow
  for a 256-event buffer before L2. We could remove
  this feature and just send the events to DAQ at a
  maximum rate of 10 kHz.

35
Low Voltage Supplies
36
Low Voltage Power Requirement of TOF FEEs.

• Maximum 110 Watts/tray _at_ 4.8 Volts _at_ tray.
• Low Noise
• Periodic and Random Distortion (PARD) lt few mVRMS
  
• Floating outputs.
• Shielded power cables (optional).
• Independent supplies/tray.
• Regulation Not critical (linear regulation on
  FEE cards).
• Remotely controlled and monitored.
• Safety Interlocked and adhere to STAR/BNL
  safety.
• Rack mounted
• Relatively low cost.
• Good efficiency.

37
Tray Low Voltage System Configuration
38
LV Electrical Connection Details
crimp lug connector AMP 52042-1
Plt110 watts
39
LV power Supply Arrangement in the Full size Racks

• Total power dissipated by each tray 110 Watts
• Total Power dissipated outside power supply
  55 Watts dissipated in each transmission cable
  (trays cables) 165 Watts
• Total heat dissipation per output channel
  (assuming 83 efficiency) 34 Watts
• Total Heat Dissipation per power supply
  mainframe (12 outputs) 408 Watts
• Total heat dissipation per full rack (6 x PL508
  or PL512) 2.45 KW
• Available cooling power/rack (3 heat
  exchangers) 3.6 KW

A full rack supplies power to 72 trays
Max. input power per PL512 chasis 3 KW (power
factor 0.96 Vmax 208 V Imax15 A)
http//www.wiener-d.com/products/20/73.html
40
Rack Location
41
Comparison of Various Power Supply Choices
The estimated costs per channel do not include
rack costs (if one includes the additional costs
then switching power supply costs are the lowest)
12 supplies/3U
9 racks
2 racks
gt24 racks
42
Details of Low Voltage Supply Connections
Cable lengths vary 80 -100
43
Power Supply Noise Characteristics
Load 100 A _at_ 5 Volts
44
Comparison of Noise Rates in TOF5Linear Supply
vs. Wiener PL508
45
TOF System Resolution from Off-Line
AnalaysisKepco Linear (red curve) vs. Wiener
(blue curve)(March 2005 Cu-Cu)
46
Slow Control for the TOF Low Voltage System
Ethernet
This figure shows tray power supplies only. There
is an additional power supply mainframe for the
Start detector FEEs and TDIG boards (and a few
spares).
47
Production Testing
48
Electronics Testing

• Bare board testing and simple stuffed board
  testing at Vendor
• Simple single board functionality testing
• Test board set of 8 TINO, 8 TDIG, and TCPU (all
  tray electronics) as a set on a dummy tray
• Test installed electronics on a tray in a cosmic
  ray setup

49
Electronics Test Plans
50
TDIG Test Setup
51
Proposed Acceptance Tests

• Proposed elements in TDIG acceptance test
• Data input on all 24 channels from TINO
• Cable delay test with generic calibration
• Operation with TCPU (ext clk, trigger pulse, data
  xfer)
• Operation with CAN bus
• Power usage under specified conditions
• Proposed elements in TCPU acceptance test
• Power usage under specified conditions
• Data transfer from TDIG
• TDC data
• Multiplicity data
• Clock, trigger to TDIG
• CAN bus
• To host PC
• Data relay from TDIG
• Multiplicity output to trigger according to a
  specified data format
• master/slave clocking

52
Crosstalk Cosmics Test
53
Crosstalk measurements
Ch. 0
START Signal
Ch. 1-7
Noise signal
HPTDC 1
Ds
Cross Talk check Analyzing shifts of
Tstart-Tstop while varying Ds
Tstart-Tstop
Ch. 23
STOP Signal
HPTDC 2
54
ALICE CAEN Cross Talk

• Stop Start Measurement
• Start Channel 0, Stop Channel 7
• Disturbing Channel on Channel 1

Stop disturbed
Start disturbed
55
Crosstalk Results
Disturbing Signal On Channel
Ch 1
Ch 2
Ch 3
Ch 4
-10ns
Ch 5
Ch 6
Ch 7
Ch 12
Different chip
Ch 1 Ch 7 Same chip
56
Crosstalk in Run 5 Data
all
1 hit
3 hits
2 hits
57
UT Cosmic Ray Testing
S1
3.00
S2
2.00

• Readout through TAMP/TINO, TDIG, and TCPU
• dT t3 (t1t2t4)/3
• Same INL correction for all HPTDCs

Gasbox
MRPC 1
MRPC 2
22.00
MRPC 3
MRPC 4
8.50
S3
58
UT Cosmic Ray Test Results
INL corrected time differences
Time-over-Threshold (ToT) Distributions (TAMP)
Slewing Corrections
Final Timing Resolutions
s(1 channel) s / v(3/2) ? average s 91ps
59
Electronics Installation
60
Electronics Items To Install

• THUB
• 4 boxes, 2 on each magnet face, about
  30inx15inx10in, 180 degrees apart from each other
• Box design and exact location still need to be
  determined
• Installation by STSG
• THUB-TCPU Interconnects
• 120 CAT5/6 cables
• Installation by TOF
• CANbus cables
• 4 cables from South platform to 4 THUB cards
• 4 cables from THUB to trays
• 120 cables from tray to tray
• Installation by TOF/STSG
• Fibers
• 4 dual fibers from THUB to DAQ
• 4 fibers to Trigger-L2 boxes

61
Electronics Items to Install(continued)

• Low Voltage Supplies
• 12 Wiener Mainframes in 2 racks
• Installation by STSG
• Low Voltage cables
• 2 voltages plus 2 sense wires per tray, already
  attached to tray at time of installation 120
  wire assemblies total
• Cut to correct length and terminated at time of
  installation
• Installation by STSG
• TCD cables
• 4 cable assemblies from TCD distribution crate to
  4 THUBs
• Installation by TOF?
• Multiplicity cables
• 120 ribbon cables from trays to trigger DSMs
• Installation by Trigger