Synthesis%20for%20Pass%20Transistor%20Logic

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Synthesis forPass Transistor Logic
Maciej Ciesielski Dept. of Electrical Computer
Engineering University of Massachusetts,
Amherst, USA ciesiel_at_ecs.umass.edu
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Overview

• Introduction
• Pass transistor basics
• Electrical considerations margin, delay, power
• Pass transistor logic (PTL)
• Pass transistor logic synthesis
• Based on conventional (CMOS) synthesis
• Logic gates implemented in PTL
• BDD-based synthesis
• BDD mapping onto Y cells Yano 96
• BDD decomposition mapping onto CMOS and PTL
  (BDS system, Yang 99

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Pass Transistor - Basics

• Works as a switch on / off
• Noise margin problem
• nMOS passes clear 0, degrades 1
• pMOS passes clear 1, degrades 0

• Need restoring logic (buffers), pass
  transmission gates

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Pass Transistor Electrical Characteristics

• Delay through a chain of pass transistors

• del RnCg 2 RnCg n RnCg RnCg(1 2
  n)
• RnCg (n 1) n / 2
• Remedy limit number of pass transistors to 3

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Pass Transistor - Applications

• Specialty, custom circuits
• XOR, etc.
• Arithmetic logic
• Custom designed arithmetic circuits
• Regularity, low area, low power
• Control logic ?
• No working methodology for logic synthesis, yet

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Conventional (CMOS) Logic Synthesis- Review -

• Targeting only CMOS logic gates
• Static no dynamic logic, no pass transistors
• Optimization metrics based on literal count
• Minimize the number of literals
• One-to-one correspondence with transistor
  signals n literals gt 2n CMOS transistors

F (A B C) ABC
Literal variable or its complement
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Conventional Logic Synthesis - Review

• Boolean expressions mapped on CMOS standard cells
• AND, OR, NAND, NOR, complex gates
• Logic functions expressed in terms of those by
  logic optimization tools (SIS, Synopsys DC, etc.)
• No MUXes, no XORs
• Large standard cell libraries
• 200-300 elements (different of inputs, power
  capability)
• Difficult to maintain, upgrade with technology
  change
• Algebraic manipulation of Boolean expressions
• Algebraic factorization (simple) ab ac a(b
  c)
• Boolean factorization (better) (a b)(a c)
  a bc

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PTL-based Logic Synthesis a Simple-minded
Approach

• Based on mapping AND/OR gates onto PTL cells
• use conventional multi-level logic optimization
• generate Boolean expressions
• map onto AND/OR gates implemented as PTL (MUXes)

B 1 F A
B 0 F Z
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Example Conventional CMOS design

• Conventional logic synthesis
• Results mapped onto CMOS gates

• F AB BC AC

( A(B C) ) (B C) AB BC
AC
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Example Conventional design PTL

• Conventional logic synthesis
• Gates mapped onto PTL gates

• F AB BC AC

( A(B C) ) (B C) AB BC
AC
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Comparison CMOS vs. PTL
F AB BC AC

• (1.88)
• 4 (1)
• 1158 ?m2 (1.36)
• 877 ps (1.35)
• 2.17 ?W/MHz (1.20)

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Conventional design with PTL- Problems -

• Simple-minded approach
• Literal count (good for CMOS), does not work for
  PTL
• Algebraic methods not compatible with MUX-based
  design
• Inefficient
• Large area, delay, power
• Need better approach, compatible with MUX concept

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PTL-based Logic Synthesis a MUX-based Approach

• Approach based on Shannon expansion
• Represent Boolean logic as a BDD
• Map BDD nodes onto PTL gates
• MUXes simple and multiple-input (Y cells)

PTL tree
Review Binary Decision Diagrams (BDD)
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Binary Decision Diagrams (BDD)

• Convenient data structure for Boolean logic
  representation and manipulation
• Decision graph, derived from Shannon expansion
• each node represents Shannon expansion along a
  variable f x fx x fx
• Represent sets of objects (states, product terms,
  etc.) encoded as Boolean functions
• Each path represents an implicant (product term)
• Reduced BDD - irredundant
• Ordered BDD - canonical
• Application to logic synthesis and verification
• Canonicity property (reduced ordered BDDs)

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BDD - Construction

• Construction of a Reduced Ordered BDD

f ac bc
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BDD Construction contd
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Application to Verification

• Equivalence of combinational circuits
• Canonicity property of BDDs
• if F and G are equivalent, their BDDs are
  identical (for the same ordering of variables)

?
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Application to Verification, contd

• Functional test generation
• SAT, Boolean satisfiability analysis
• to test for H 1 (0), find a path in the BDD to
  terminal 1 (0)
• the path, expressed in function variables, gives
  a satisfying solution (test vector)

H
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Application to Synthesis

• BDD node simple multiplexer (MUX)

F x Fx x Fx
x
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Application to Synthesis (simple-minded approach)

• Represent each BDD node as a MUX, implemented in
  PTL

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PTL-based Logic Synthesis- Problems -

• Ineffective for larger circuits
• too large, too slow, too many MUXes
• pass transistor chains are too long
• need separating buffers
• need methodology for synthesizing circuits from
  their BDDs

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Logic Synthesis based on Pass Transistor Logic

• Introduce a few PTL cells
• easy to maintain cell library

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Basic CMOS and PTL cells
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Characteristics - PTL vs. CMOS cell
F (A B C) ABC
Transistor count Cell count Area Delay Power
6 (1) 1 (1) 329 ?m2
(1) 295 ps (1) 0.91 ?W/MHz (1)
13 (2.17) 3 (3) 579 ?m2
(1.75) 465 ps (1.58) 0.96 ?W/MHz
(1.05)
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PTL-based Logic Synthesis a multi-input
MUX-based Approach

• Based on multi-input MUXes (Y cells)

F (ACB AB) AB BC AC
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MUX-based Approach

• Compare to conventional approach with PTL gates
• (numbers relative to CMOS)

Transistor count Cell count Area Delay Power

• (1.88)
• 4 (1)
• 1158 ?m2 (1.36)
• 877 ps (1.35)
• 2.17 ?W/MHz (1.20)

13 (0.81) 3 (0.75) 579 ?m2 (0.68) 465 ps
(0.71) 0.96 ?W/MHz (0.53)
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PTL Synthesis Flow Yano 96

• Express Boolean logic as shared, multi-output BDD
• Partition BDD into smaller sub-trees, isomorphic
  with Y cells
• Map each sub-tree onto a Y cell
• Insert buffers at the Y-cell boundaries
• this keeps pass transistor chains limited to 2 (Y
  tree height)
• Fix circuit polarity by propagating inverters
• Adjust inverter power (P2,4,etc) according to
  cell load

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Y-cell based PTL Synthesis - Example

• Create shared BDD
• f w x (y z yz)

g w (y z yz)
Y1
Y2

• Partition BDD into sub-trees and map each
  sub-trees to a Y cell

Y1

• Note Cell type depends on the logic implemented,
  not just on the number of variables/inputs

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Example PTL mapping

• f w x (y z y z)
• g w (y z y z)

Y2
Y1
Y1
f w x (y z y z) w x (y z
y z)
g w w (y z y z) w (y z y z)
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PTL Synthesis - Results

• Impressive results for control logic and
  arithmetic circuits
• improvement in area, delay and power !
• need BDD synthesis partitioning methodology
• use CMOS gates as natural buffers?
• New research (BDS) mixing CMOS with PTL