Progressive Register Allocation for Irregular Architectures - PowerPoint PPT Presentation

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Progressive Register Allocation for Irregular Architectures

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Examples: x86, 68k, ColdFire, ARM Thumb, MIPS16, V800, ... Register Usage Restrictions. Instructions may prefer or require a specific subset of registers ... – PowerPoint PPT presentation

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Title: Progressive Register Allocation for Irregular Architectures


1
Progressive Register Allocation for Irregular
Architectures
  • David Koes
  • dkoes_at_cs.cmu.edu
  • Seth Copen Goldstein
  • seth_at_cs.cmu.edu
  • March 23, 2005

2
Irregular Architectures
  • Few registers
  • Register usage restrictions
  • address registers, hardwired registers...
  • Memory operands
  • Examples
  • x86, 68k, ColdFire, ARM Thumb, MIPS16, V800,
    various DSPs...

3
Fewer Registers ? More Spills
  • Used gcc to compile gt10,000 functions from
    Mediabench, Spec95, Spec2000, and
    micro-benchmarks
  • Recorded which functions spilled

4
Register Usage Restrictions
  • Instructions may prefer or require a specific
    subset of registers
  • x86 multiply instruction
  • imul edx,eax // 2 byte instruction
  • imul edx,ecx // 3 byte instruction
  • x86 divide instruction
  • idivl ecx // eax edxeax/ecx

5
Memory Operands
  • Load/store not always needed to access variables
    allocated to memory
  • depends upon instruction
  • still less efficient than register access
  • addl 8(ebp), eax
  • vs
  • movl 8(ebp), edx
  • addl edx, eax

6
Register Allocation Challenges
  • Optimize spill code
  • with few registers, spilling unavoidable
  • Model register usage restrictions
  • Exploit memory operands
  • affects spilling decisions

7
Previous Work
8
Our Goals
  • Expressive
  • Explicitly represent architectural irregularities
    and costs
  • Proper model
  • An optimum solution results in optimal register
    allocation
  • Progressive solution algorithm
  • more computation ? better solution
  • decent feasible solution obtained quickly
  • competitive with current allocators

9
Multicommodity Network Flow (MCNF)
10
Modeling Usage Constraints
int foo(int a, int b, int c) a ab
return a/c
not quite right
11
Modeling Spills and Moves
int foo(int a, int b, int c) a ab
return a/c
12
Modeling Stores
  • Simple approach flawed
  • doesnt model memory persistency

13
Register Allocation as MCNF
  • Variables ? Commodities
  • Variable Usage ? Network Design
  • Nodes ? Allocation Classes (Reg/Mem)
  • Registers Limits ? Node Capacities
  • Spill Costs ? Edge Costs
  • Variable Definition ? Source
  • Variable Last Use ? Sink

14
Solving an MCNF
  • Integer solution NP-complete
  • Use standard IP solvers
  • commercial solvers (CPLEX) are impressive
  • Exploit structure of problem
  • variety of MCNF specific solvers
  • empirically faster than IP solvers
  • Lagrangian Relaxation technique

15
Lagrangian Relaxation Intuition
  • Relaxes the hard constraints
  • only have to solve single commodity flow
  • Combines easy subproblems using a Lagrangian
    multiplier
  • an additional price on each edge

Example edges have unit capacity
16
Solution Procedure
  • Compute prices using iterative subgradient
    optimization
  • converge to optimal prices
  • At each iteration, greedily construct a feasible
    solution using current prices
  • allocate most expensive vars first
  • can always find an allocation

17
Solution Procedure
  • Advantages
  • have feasible solution at each step
  • iterative nature ? progressive
  • Lagrangian relaxation theory provides means for
    computing a lower bound
  • Can compute optimality bound
  • Disadvantages
  • No guarantee of optimality of solution

18
Evaluation
  • Replace gccs local allocator
  • Optimize for code size
  • easy to statically evaluate
  • Evaluate on MediaBench, MiBench, SpecInt95,
    SpecInt2000
  • consider only blocks where local allocation is
    interesting (enough variables to spill)

19
Behavior of Solver
20
Proven Optimality
21
Comprehensive Results
artifact of interaction with gcc
22
Progressive Nature
23
Contributions
  • New MCNF model for register allocation
  • expressive, can model irregular architectures
  • can be solved using conventional ILP solvers
  • Progressive solution procedure
  • decent initial solution
  • maintains feasible solution
  • improves solution over time
  • no optimality guarantees

Progressive
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