Alternative Architectures (Chapter 9)

1
Alternative Architectures(Chapter 9)

• CS147 section 03
• Ke-Huan Chou

2
Topics

• RISC machines
• CISC machines
• RISC vs. CISC
• Register Windows Sets

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Some History About RISC

• The earliest attempt to make a chip-based RISC
  CPU was by IBM in 1975 IBM 801
• Then UC Berkerley started their RISC project in
  1980 RISC-I
• Stanford also had their RISC project started in
  1981 MIPS

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Reduced Instruction Set Computer (RISC)

• The original idea for RISC machine is to provide
  a set of minimal instructions that could do all
  the essential operations (move data, arithmetic
  logic unit operations, branching)
• Only load and store instructions are
  permitted access to external memory, all other
  instructions are limited to internal registers.
• The goal for RISC machine is to make the
  instructions so simple that they could easily be
  pipelined.

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Some Typical Characteristics of RISC

• Emphasis on software
• It has small instruction set
• It uses more instructions in programs
• The instructions take less time to decode
• It has simple addressing modes
• It spends more transistors on memory registers
• It has few data types in hardware

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What about CISC?

• Complex Instruction Set Computer, or CISC for
  short
• CISC were motivated by the high cost of memory
  because it was designed to use less memory and
  disc storage in each program
• Each instruction should to do as much work as
  possible, which also means that it is designed to
  minimize the number instructions in each program

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Some Typical Characteristics of CISC

• Emphasis on hardware
• It has large instruction set
• It has less instruction in a program
• The instructions are more complex
• It takes longer to decode the instructions
• It has complex data types in hardware

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How to quantify the differences between RISC and
CISC?

• We can use the following equation to calculate
  the computer performance and compare the results
  between RISC and CISC

Program execution time is directly proportional
to clock cycle time, number of cycles for each
instruction, and the number of instructions in
the program
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RISC vs. CISC (page468 table 9.1)

• Single register set, typically 6 to 16 registers
  total
• One or two register operands allowed per
  instruction (add R1, R2)
• Parameter passing through inefficient off-chip
  memory
• has Multiple-cycle instructions
• Microprogrammed control
• Less pipelined
• Many complex instructions
• Variable length instructions
• Complexity in microcode
• Many instructions can access memory
• Many addressing modes

• - Multiple register sets, often consisting of
  more than 256 registers
• - Three register operands allowed per instruction
  (add R1, R2, R3)
• - Parameter passing through efficient on-chip
  register windows
• - has Single-cycle instructions (except for load
  and store)
• - Hardwired control
• - Highly pipelined
• Simple instructions that are few in number
• Fixed length instructions
• Complexity in compiler
• Only load and store instructions can access
  memory
• Few addressing modes

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A Simple Example
5 X 10 ?
RISC way
CISC way
mov ax, 0 mov bx, 10 mov cx, 5 Begin add ax,
bx loop Begin
mov ax, 10 mov bx, 5 mul bx, ax
1010101010 50
10 X 5 50
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Total Clock Cycle for the Example
RISC Total clock cycles (3 mov X 1 clock
cycle) (5 add X 1 clock cycle) (5 loop X 1
clock cycle) 13 clock cycles
CISC Total clock cycles (2 mov X 1 clock
cycle) (1 mul X 30 clock cycle) 32 clock
cycles
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Another Example
Main Memory
Suppose we want to multiply 2 numbers that stored
in the main memory 2 4
and 4 3 (Row) (Column)
Registers
Execution unit
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The Instructions Might Look Like This
RISC way
CISC way
LOAD A, 24LOAD B, 43PROD A, BSTORE 24, A
MUL 24, 43
Thats it. The instruction will load the two
numbers in those two areas in main memory and put
them in separate registers, and it will do
multiplication of those two numbers and store the
result in the register
First, Load the number stored in 24 put it in
register A. Then load the number stored in 43
and put it in register B. Get the product of A
and B. Store the result back to 24
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RISC vs. CISC

• From the first example, we can see that in RISC
  machine, the total clock cycle is shorter than
  the total clock cycle in CISC machine
• Even though there are more instructions in RISC
  than in CISC, each RISC instructions only
  requires one clock cycle to execute, and CISC
  instructions require more clock cycles because
  they are more complex.
• From the second example, we can see that in RISC
  machine, only Load and Store instructions can
  access to the main memory.
• Because the instruction in CISC is really short,
  it only need a little bit of RAM to store the
  instructions

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Register Windows Sets

• A way to use the registers efficiently
• A typical RISC architectures has 16 register sets
  (or windows), and there are 32 registers in each
  set
• The CPU is restricted to operate only one window
  at any time, which means that there are only 32
  registers available
• The registers set can be divided into
• - Global registers common to all windows.
• - Local registers local to the current window
• - Input registers overlaps with the preceding
  windows output registers
• - Output registers overlaps with the next
  windows input registers.
• - Current window pointer (CWP) points to the
  register window set to be used at any
  given time

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An Example
Procedure One is calling Procedure Two

• When Procedure One calls Procedure Two, any
  parameters that need to be passes are put into
  the output register in Procedure One
• When Procedure Two starts executing, the output
  register in Procedure One becomes the input
  register in Procedure Two

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Diagram (page 467 figure 9.1)
CWP 8
Procedure One
CWP 24
overlap
Procedure Two
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References

• http//en.wikipedia.org/wiki/CDC_6600, Wikipedia
  10/19/09
• http//en.wikipedia.org/wiki/Reduced_instruction_s
  et_computer, Wikipedia 10/19/09
• http//en.wikipedia.org/wiki/Complex_instruction_s
  et_computer, Wikipedia 10/19/09
• http//www.museumwaalsdorp.nl/computer/en/comp781b
  E.html, museumwaalsdorp
• http//cse.stanford.edu/class/sophomore-college/pr
  ojects-00/risc/risccisc/index.html, by Crystal
  Chen, Greg Novick and Kirk Shimano
• http//www.pic24micro.com/cisc_vs_risc.html,
  PIC24F Microcontrollers hands-on tutorials, real
  time embedded projects, 10/19/09