Camera Auto Focus

1
Camera Auto Focus

• Presentation 12, April 25th, 2007

Team W1 Tom Goff (W11) David Hwang (W12) Kate
Killfoile (W13) Greg Look (W14) Design Manager
Bowei Gai Project Goal Design a low-power, small
auto focus chip for a camera or other
hand-held device
2
Introduction

• Explanation of general camera operation and how
  focusing works
• Brief history / overview of existing camera
  autofocus methods
• Snazzy animation

Dave
3
Usage / Target Market

• Digital Cameras, Security Cameras, Home Video
  Cameras

Dave
4
Fuzzy-Logic Autofocus

• Overview of fuzzy-logic algorithm for determining
  lens-armature movement
• sharpness index differential (di) and average
  gain (ag) computed seperately
• Resulting values fed into fuzzy-logic chip to
  determine final outcomes (graph of di ag zones)

Dave
5
Translation to Hardware

• Computation requires floating-point
  justification of 145 field split
• Fuzzy Logic means a series of summed products
  need a floating point multiplier and floating
  point adder
• Explain optimization of trading speed for size by
  reusing one multiplier and adder

Dave
6
Other Design Goals

• Explain other goals which impacted architecture
  space, low power, speed, etc.
• Compare to existing solutions

Dave
7
Overall Architecture

• Picture of global signal flow, schematic and
  layout
• Neat animation of signal flow
• History of past floorplan designs

Greg
8
Integer Adder Architecture

• Explain choice of (integer) adder based on
  previously stated design decisions
• Comparison to other considered designs

Greg
9
Integer Multiplier Architecture

• Architecture decisions go here
• Alternatives considered, pros/cons

Greg
10
FP Adder Architecture

• Floating Point decisions drove fp adder
  architecture decisions
• Need precision of denormalized numbers, adds lots
  of complexity
• Dont need rounding, avoids a lot of complexity
• Fields are small enough that we can determine
  leading zeroes combinationally, saves a lot of
  time

Greg
11
FP Multiplier Architecture

• Lots of module re-use from the fp adder
• Moved from two two-input multipliers to one
  three-input multiplier can save on the pre- and
  post-multiplication logic as we only need to
  combine exponents / normalize once

Greg
12
Verification

• Layout of full algorithm based on inputs
• C programs to execute algorithm, as well as
  sub-programs to deal with conversions from 32-bit
  floating point to our 10-bit format
• More C to simulate our floating point modules

K8
13
Verification

• Wrote structural Verilog and measured against C
  programs able to perform exhaustive testing to
  prove matching
• Took structural Verilog and created schematics in
  Virtuoso tested general and edge cases to prove
  correspondence

K8
14
Verification

• Verified module layouts against schematics at
  every level
• Ran analog simulations on the layouts to test
  general and edge cases against expected outputs
  from the schematic

K8
15
Layout Stuff

• Neat pictures of our layout layers,
  poly/metal1/2/3/4 and transistor/layer density

Tom
16
Simulation Results

• Show results at each stage and how they match up
  to the algorithm
• Go through one full pass and show numbers and
  accumulation
• Show delay of critical path and discuss FSM timing

Tom
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Final Specifications

• Present final chip specs, measure against initial
  goals
• Area/Density
• Speed
• Power Consumption
• Relate to existing solution

Tom
18
Questions?
All