Camera Auto Focus

1
Camera Auto Focus

• Presentation 6, February 28th, 2007

Team W1 Tom Goff (W11) David Hwang (W12) Kate
Killfoile (W13) Greg Look (W14) Design Manager
Bowei Gai Project Goal Design a low-power, small
auto focus chip for a camera or other
hand-held device
2
Status

• Last Time
• Exhaustive simulations
• Schematic
• This Week
• Rigorous schematic testing
• Control logic structural Verilog
• Sub-module layout
• In Process
• Layout
• Schematic of control logic
• Unfinished
• Extraction, LVS, post-layout simulation

3
Design Decisions

• Split up FSM logic (detailed later)
• Decided on an adder
• Settled on sense amp registers
• Crazy optimizations of schematic

4
Updated Transistor Count
Component Full Chip Count
AG Preprocessor 2,274
Delta I Preprocessor 2,624
FP multiplier 5,832
FP adder 994
Power control 1,000
Buffers 2,000
Total 17,182
Still fluctuating
5
Control Logic FSMs
6
FSM1
Next state
Global rst
Next State Logic
Pulse Generator
Compare 10
Enable
Reset Clock
Output Logic
Reg1
Reg0
Enable next FSM
7
FSM2
Next state 20
Global rst
More complicated next state logic
Pulse Generator
Compare 32
Enable FSM1
Reset Clock
Output Logic
Mux Lines 60
Reg3
Reg2
8
Bus Widths
Global rst
FSM1
FSM2
Enable FSM2
Bus Path Bits
To FSM1 3
To FSM2 2
To Counter 1
Clk
Compare 0
Reset Line
Compare 1
Counter?0
9
Schematic Verification

• Every module completely tested
• Excluding power logic

10
Layout Progress
Modules Layout Completed
Basic gates 100
Registers 100
Muxes 100
Adders 25
Shifters 0
Integer multiplier 0
11
Full Adder
12
Full Adder
13
Registers
14
Registers
15
Muxes
16
Next Steps

• Sleep briefly
• Continue laying out modules
• Complete control logic schematic

17
Problems

• Pass transistors make for terrible layouts
• Shared libraries are a pain
• Selfish cluster users crowding our space many
  deaths
• Difficult to synchronize FSMs

18
Questions
19
References

• None this week