VLSI Design Project Audio Steganography

1
VLSI Design ProjectAudio Steganography

• Implementation Review Slideshow
• Ben Doherty Chris Campetti
• Jeremy Gummeson Phil Murray

2
Statistics

• PRNG Auto-Correlation
• 10,000 samples
• Maximum over a span of 1000 with a lag of 1
  0.0363
• This indicates very little correlation
• Power consumption for entire design
• Probabilistic values given by Power Compiler
• Dynamic 384.228mW
• Leakage 8.730uW
• Power is most heavily consumed in register file
  (157mW/6.8uW) and 3DES core (136mW/0.5uW)

3
Initial Power Analysis

• Synopsys Power Compiler
• Default power analysis is done by probabilistic
  flipping of nodes throughout design
• Good for average case scenarios, but has little
  to do with power consumption during usage
• Still trying to flesh out input vector methods
• SAIF files Backward/Forward SAIF
• Verilog-XL may be able to generate these

4
Design Iterations SPI

• First design (V0) had a single FSM, which was
  clocked on both SPI_CLK edges
• Would verify under Verilog-XL, but not synthesize
  properly (lack of dual-edge registers)
• Second design split FSM into two separate FSMs
• One operated Regfile control signals, the other
  shifted bits in/out
• Significant improvement of power/area

5
Design Iterations Register File

• V0 wasted a lot of area on multiple large
  multiplexors
• always _at_(posedge write_latch) begin
• if(REG_wr0 1'b1)
• reg_wrdata lt REG_write0
• else if(REG_wr1 1'b1)
• reg_wrdata lt REG_write1
• end
• V1 had code to EXPLICITLY infer specific
  multiplexors for input data registers
• wire 10 wrdata_MUX_sel
• assign wrdata_MUX_sel REG_wr0,REG_wr1
• wire FILEWIDTH-10 wrdata_mux
• assign wrdata_mux (wrdata_MUX_sel 2'b00 ?
  0
• wrdata_MUX_sel 2'b01 ? REG_write0
• wrdata_MUX_sel 2'b10 ? REG_write1 0)
• // The write data latch register
• always _at_(posedge write_latch)

6
Design Iterations - PRNG

• V0 Multiple Driver issue on load register
• Again, would simulate properly in Verilog-XL, but
  would cause synthesis errors during compile
  (Assumed a wired-AND)
• V1 Inferred shift register with asynchronous
  load
• always _at_(posedge read_in or posedge clk) begin
• if(read_in 1'b1)
• shift lt key_in

7
Area/Power Contributions
POWER
AREA
8
Cell References
9
Who Did What?

• Ben
• REGFILE and SPI interface, PRNG V1
• Verification test benches
• Design analysis power, area, cell references
• Chris
• CODEC
• Initial PRNG
• Test bench and Analysis
• Preliminary design analysis
• Jeremy
• Mostly CODEC module development
• Verification of CODEC
• Phil
• Layout, schematics
• Some design analysis

10
Design Flow
11
Modular Floorplan
12
What we have so far

• Complete design, including
• Pseudo-dual port register file memory
• SPI Interface
• Steganography CODEC
• PRN generator
• 3DES module from OpenCores
• Design has been laid out and verified

13
What we plan on doing

• FPGA implementation on DE2 board
• Modular IC layout
• More thorough power analysis
• More thorough verification
• RTL
• CODEC bugs/improvements (V2)