Pengantar Organisasi Komputer

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IKI20210Pengantar Organisasi KomputerKuliah
Minggu ke-5b Prosesor
Sumber1. Hamacher. Computer Organization,
ed-4.2. Materi kuliah CS152, th. 1997, UCB.
9 Oktober 2002 Bobby Nazief (nazief_at_cs.ui.ac.id)J
ohny Moningka (moningka_at_cs.ui.ac.id) bahan
kuliah http//www.cs.ui.ac.id/iki20210/
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• Waktu Eksekusi

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Waktu Eksekusi Gate Delay

• When input 0 ? 1, output 1 ? 0 but NOT instantly
• Output goes 1 ? 0 output voltage goes from Vdd
  (5v) to 0v
• When input 1 ? 0, output 0 ? 1 but NOT instantly
• Output goes 0 ? 1 output voltage goes from 0v to
  Vdd (5v)
• Voltage does not like to change instantaneously

Voltage
1 gt Vdd
0 gt GND
Time
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Waktu Eksekusi Series Connection
Vdd
V1
Vin
G1
G2
G1
G2
C1
Voltage
Vdd
V1
Vout
Vin
Vdd/2
d1
d2
GND
Time

• Total Propagation Delay Sum of individual
  delays d1 d2
• Capacitance C1 has two components
• Capacitance of the wire connecting the two gates
• Input capacitance of the second inverter

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Waktu Eksekusi Registers Delay
Clk

• Setup Time Input must be stable BEFORE the
  trigger clock edge
• Hold Time Input must REMAIN stable after the
  trigger clock edge
• Clock-to-Q time
• Output cannot change instantaneously at the
  trigger clock edge

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Waktu Eksekusi
R2out, Add, Zin
Turn-on time for 3-state driver
Transmission time
Propagation delay through ALU
Setup time
Hold time
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• Langkah-langkah
• Pengeksekusian Instruksi

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Tahapan Eksekusi Instruksi

• Instruksi
• Add R1,(R3) R1 ? R1 MR3
• Langkah-langkah
• Fetch instruksi
• PCout, MARin, Read, Clear Y, Set carry-in to ALU,
  Add, Zin
• Zout, PCin, WMFC
• MDRout, IRin
• Fetch operand 1 (isi lokasi memori yg ditunjuk
  oleh R3)
• R3out, MARin, Read
• R1out, Yin, WMFC
• Lakukan operasi penjumlahan
• MDRout, Add, Zin
• Simpan hasil penjumlahan di R1
• Zout, R1in, End

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1. Fetch instruksi
Add R1,(R3) R1 ? R1 MR3
Control lines
Address lines
Data lines
00000000
Add
1
Carry-in
PC1
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2. Fetch operand 1
Add R1,(R3) R1 ? R1 MR3
Address lines
Data lines
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3. Lakukan operasi penjumlahan
Add R1,(R3) R1 ? R1 MR3
Address lines
Data lines
Add
Carry-in
Zin
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4. Simpan hasil penjumlahan
Add R1,(R3) R1 ? R1 MR3
Address lines
Data lines
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Tahapan Eksekusi Branching

• Unconditional
• PCout, MARin, Read, Clear Y, Set carry-in to ALU,
  Add, Zin
• Zout, PCin, WMFC
• MDRout, IRin
• PCout, Yin
• Offset-field-of-IRout, Add, Zin // PC ? PC
  Offset
• Zout, PCin, End
• Conditional (contoh branch-on-negative)
• PCout, MARin, Read, Clear Y, Set carry-in to ALU,
  Add, Zin
• Zout, PCin, WMFC
• MDRout, IRin
• PCout, Yin , If N0 then End // take the branch?
• Offset-field-of-IRout, Add, Zin // PC ? PC
  Offset
• Zout, PCin, End

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• Pengendalian Eksekusi Instruksi
• Hardwired Control

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Interaksi Control ? Datapath

• STEP CONTROL SIGNALS
• 1. PCout, MARin, Read, Clear Y, Set carry-in to
  ALU, Add, Zin
• 2. Zout, PCin, WMFC
• 3. MDRout, IRin
• 4. R3out, MARin, Read
• 5. R1out, Yin, WMFC
• 6. MDRout, Add, Zin
• 7. Zout, R1in, End

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Organisasi Unit Pengendali
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Pemisahan Decoder Encoder
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Contoh Struktur Encoder untuk sinyal Zin

• Fungsi Logika
• Zin T1 T6 ? ADD T5 ? BR
• Zin akan terjadi pada
• T1 untuk setiap instruksi (instruksi
  berikut PC1)
• T5 untuk instruksi ADD
• T6 untuk instruksi BR

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Interaksi Prosesor ? Memori
t2
t3
t4
t5
t1
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Implementasi Unit Pengendali pada VLSI

• PLA (Programmable Logic Array)
• Struktur gerbang logika yang terdiri dari
  kelompok AND OR
• Pola interkoneksi yang teratur sehingga padat ?
  VLSI

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Struktur Internal PLA
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Interaksi Memori ? Control,Datapath
Control
Ideal Instruction Memory
Control Signals
Conditions
Instruction
Rd
Rs
Rt
5
5
5
Instruction Address
A
Data Address
Data Out
32
Rw
Ra
Rb
32
Ideal Data Memory
32
Registers
Next Address
Data In
B
Clk
Clk
32
Datapath