Project ARIES

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Project ARIES

• Advanced RAM Integration for Efficiency and
  Scalability
• Presented by the 8th floor buttheads
• (pun intended)

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Talk Overview

• Motivation and research goals
• Previous work
• System description
• Current work
• Research Opportunities

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Motivation - System Level

• Many applications have massive memory and/or
  computational requirements
• graphics, CAD, physical simulation, factoring,
  etc.
• Current parallel systems have severe limitations
• difficult to program
• poor network performance
• insufficient scalability
• There is a need for programmable systems scalable
  to 1M processors and beyond

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Motivation - Architecture

• Transistor counts have increased 1000x in 20
  years
• 1978 29K in Intel 8086
• 1999 23M in NVIDIA GeForce 256

8086

• Suppose someone gave you 100M transistors and you
  had never seen a load-store architecture. What
  would you build?
• There is a need for designs scalable to 1G
  transistors and beyond

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Motivation - Area Efficiency

• In modern processors lt 25 of chip area devoted
  to useful work (red areas on die shot)
• gt 75 devoted to making the 25 faster
• Even the 25 is bloated due to
• large instruction sets
• complex superscalar design
• ...not necessarily a bad thing

K7 Die Photo
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Motivation - Scalability

• Today
• 1-4 processors per die
• Use available area to make processor fast
• complicated designs

• Tomorrow
• N processors per die
• Use available area for lots of processors
• simple designs

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Motivation - RAM Integration

• Logic and DRAM on a single die provides
• lower latency access to memory (2x)
• much higher bandwidth (10x)
• What architectural features are enabled by this
  technology?
• SRAM-tagged DRAM
• Transactional memory
• Forwarding pointers

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Research Goals

• Highly programmable parallel system
• language
• compiler
• operating system
• architecture
• Manage huge data sets
• Area efficient architecture
• Integration of processor and memory

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Architectural Goals

• Fast general purpose processor
• 1 GFLOP/processing node
• High performance network
• high bandwidth (4GB/s at each node)
• low latency (10ns across a 1000 node system)
• Compilability
• Scalability
• up to 1,000,000 nodes

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Talk Overview

• Motivation and research goals
• Previous work
• System Description
• Current work
• Research Opportunities

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Previous Work - Processors

• Bill Dally
• J-Machine
• M-Machine
• Imagine
• Anant Agarwal
• Alewife
• RAW
• NYU Ultracomputer

• Hydra
• VLIW stuff
• KSR1
• NuMachine
• Hydra
• Tera
• IBM Power4

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Previous Work - Networks

• Tom Knight
• Metro
• Bill Dally/John Poulton
• 4GB/s
• Craylink
• SGI

• Charles Leiserson
• FAT trees
• SCI
• HiPPi
• CM-5
• Myranet
• Artic

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Previous Work - Cache

• SHASTA
• DASH
• FLASH
• LimitLESS

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Previous Work - Languages

• NESL

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Other Previous Work

• Capabilities
• Guarded Pointers (Dally)
• Containment
• IRAM
• IStore

• SimOS
• Beowulf
• Active Pages

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Talk Overview

• Motivation and research goals
• Previous work
• System description
• Current work
• Research Opportunities

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System Description

• Distributed shared memory machine
• No caching of remote data
• Single shared virtual address space
• Large collection of processor-memory nodes
• High Performance FAT Tree network

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System Description

• OS
• Memory management
• threads
• language
• ???

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Top-Level View

• Bunnie should make this slide.. Bunch of cabinets
  containing processor and network boards 1 disk
  drive per network board high speed serial links
  enough wire to tether the moon to tech square.

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Chip-Level View

• array of processor-memory nodes connected by
  on-chip network
• high speed signaling technology exists (Dally) to
  provide large off-chip bandwidth
• e.g. 256 pin pairs at 2Gb/s each 512 Gb/s

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Processor-Memory Node
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Processing element

• 128 bit multi-context VLIW processor
• Four functional units
• IEEE floating point
• Hardware enforced capabilities
• Hardware Macros???

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Simple Silicon

• No dynamic superscalar issue
• No out of order issue
• No register renaming
• No branch prediction
• No speculative execution
• No remote-data caching

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Key Features

• Fast fault tolerant network
• blah blah blah
• Augmented DRAM
• SRAM tagged DRAM
• fast searching for marked data
• high performance GC
• experimental versioning
• Hardware page tables

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Key Features

• Fixed virtual address ? node mapping
• Eliminates global tables
• Multi-striped address ? node mapping
• Stripe contiguous addresses across nodes at any
  power of two granularity
• Memory efficient guarded pointers
• Power-of-two schemes waste up to 50 of the
  virtual address space

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Talk Overview

• Motivation and research goals
• Previous work
• System description
• Current work
• Research Opportunities

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Hardware Design Effort

• Node design
• processor
• memory system
• Network design
• routing protocol
• topology
• Cycle accurate simulator

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Prototyping System

• Simulator for complex system issues
• not practical to do an accurate, pure software
  simulation of a massively parallel processor
• Evaluation of experimental architectural features
  in a realistic environment
• network topologies
• language design
• hardware support for programming features

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Prototyping System

• Modular design
• easily reconfigure a single design for multiple
  network topologies by recabling and
  redistributing processor and network cards
• network can be adapted for other
  performance-oriented platforms
• enable collaboration between multiple research
  groups in different research institutions

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Modular Design
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Prototype Node

• Features for fast debug, profiling,
  reconfiguration
• Architecture to enable experimentation with novel
  memory architectures and domains of execution

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Prototype Node
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Language Design

• Communication intensive programming
• Leverage data snapshots for migratability
• e.g. function calls
• Blah blah blah

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Garbage Collection

• Fast area local GC
• Data migration
• Paging friendly
• Blah blah blah

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Talk Overview

• Motivation and research goals
• Previous work
• System description
• Current work
• Research Opportunities

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Research Opportunities

• Processor evaluation
• hand coded sample apps
• performance at various design points
• Language design/evaluation
• expresses parallelism and communication
• programmability vs. compilability

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Research Opportunities 2

• Compiler Design
• C compiler
• PSCHEME compiler
• VLIW scheduling
• Operating System Design
• Thread management, page management, memory
  management, etc. etc. etc.

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Research Opportunities 3

• Alternative Execution Domains
• secure computing
• efficient dynamic typing
• transactional/speculative computing
• dataflow