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Complex Programmable Logic Device (CPLD)

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A type of storage device in which the data is determined by ... Wired-AND with PROMs. Arindam Mukherjee, ECE Dept., UNCC. Product term and distributor array ... – PowerPoint PPT presentation

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Title: Complex Programmable Logic Device (CPLD)


1
Complex Programmable Logic Device (CPLD)
2
EPROM
A type of storage device in which the data is
determined by electrical charge stored in an
isolated ("floating") MOSFET. The isolation is
good enough to retain the charge almost
indefinitely (more than ten years) without an
external power supply. The EPROM is programmed
by "injecting" charge into the floating gate,
using a technique based on the tunnel effect.
This requires higher voltage than in normal
operation (usually 12V - 25V). The floating gate
can be discharged by applying ultraviolet light
to the chip's surface through a quartz window in
the package, erasing the memory contents and
allowing the chip to be reprogrammed.
3
EPROM
The fraction of memory states to flip (0 to 1)
plotted as a function of the duration of
exposure to UV radiation. The dotted line
represents the shift in the curve due to a
passive exposure of the device to ionizing
radiation before the UV run.
4
EEPROM (electrically erasable)
5
Flash EEPROM (electrically erasable)
6
Wired-AND with PROMs
7
Product term and distributor array
8
Macro Cell PALCE16V8
9
Logic Block of PALC22V10
10
PIM
programmable interconnects pulled HIGH
MC1
LB
MCn
to prod uct term array
sense amplifiers
11
CPLD Schematic
12
Timing Diagrams combinational o/p
13
Timing Diagrams registered o/p
14
Timing Diagrams latched o/p
15
Timing Diagrams registered i/p
16
Timing Diagrams latched i/p
17
Timing Diagrams latched i/p and o/p
18
Timing Diagrams reset
19
Timing Diagrams preset
20
Timing Diagrams feedbacks
combinational logic
tco2
combinational logic
signals
tscs
combinational logic
21
Maximum operating frequency
22
CY7C374i - Features
  • 128 macrocells in eight logic blocks
  • 64 I/O pins
  • 5 dedicated inputs including 4 clock pins
  • In-System Reprogrammable (ISR) Flash
    technology
  • JTAG interface
  • Bus Hold capabilities on all I/Os and dedicated
    inputs
  • No hidden delays
  • High speed
  • fMAX 125 MHz
  • tPD 10 ns
  • tS 5.5 ns
  • tCO 6.5 ns
  • Fully PCI compliant
  • 3.3V or 5.0V I/O operation
  • Available in 84-pin PLCC, 84-pin CLCC, and
    100-pin TQFP packages
  • Pin compatible with the CY7C373i
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