chapter six transparency

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Chapter 7 Parallel I/O Ports
The 68HC11 Microcontroller
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Basic I/O Concepts
Peripheral devices Pieces of equipment that
exchange data with a computer. Examples include
switches, light-emitting diodes, cathode-ray
tube screens, printers, modems, keyboards,
and disk drives. Interface chip - A chip whose
function is to synchronize data transfer between
the CPU and I/O devices. - An interface may
consist of control registers, status registers,
data direction registers, latches, and control
circuitry. - An interface chip has pins that are
connected to the CPU and I/O port pins that are
connected to the I/O devices. - Each interface
chip has a chip enable signal input or inputs,
when asserted, allow (s) the interface chip to
react to the data transfer request. - Data
transfer between an I/O device and the CPU can be
proceeded bit-by-bit or in multiple bits.
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Address bus
Address decoder
From input device
To output device
CE
CE
CE
CE
R/W
Interface Chip 1
Interface Chip 2
ROM
SRAM
Microprocessor
Data Bus
Figure 7.1 A Simple Computer with RAM, ROM, and
Input and Output Ports
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I/O Schemes
1. Isolated I/O scheme - The microprocessor has
dedicated instruction for I/O operations - The
microprocessor has separate address space for I/O
devices 2. Memory-mapped I/O scheme - The
microprocessor uses the same instruction set for
I/O operations - The I/O devices and memory
components are resident in the same memory space
I/O Transfer Synchronization
The role of an interface chip
handshake or strobe signals
Control signals
I/O device electronics
Interface chip
(such as interrupt or R/W)
Microprocessor
Data Bus
Figure 7.2 The role of an interface chip
5
Synchronizing the Microprocessor and the
Interface Chip The polling method 1. for input
-- the microprocessor checks a status bit of the
interface chip to find out if the interface has
received new data from the input device. 2. for
output -- the microprocessor checks a status bit
of the interface chip to find out if it can
send new data to the interface chip. The
interrupt-driven method 1. for input -- the
interface chip interrupts the microprocessor
whenever it has received new data from the input
device. 2. for output -- the interface chip
interrupts the microprocessor whenever it can
accept new data from the microprocessor.
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Synchronizing the Interface Chip and the I/O
Devices Brute-force method -- useful when the
data timing is unimportant 1. for input --
nothing special is done. The microprocessor
reads the interface chip and the interface chip
returns the voltage levels on the input port pins
to the microprocessor. 2. for output -- nothing
special is done. The interface chip places the
data that it received from the microprocessor
directly on the output port pins. The strobe
method -- a strobe signal is used to indicate
that data are stable on I/O port pins 1. for
input -- the interface chip latches the data into
its data register using the strobe signal. 2. for
output -- the interface chip places the data on
port pins that it received from the
microprocessor and asserts the strobe signal.
The output device latches the data using the
strobe signal. The handshake method -- used
when timing is crucial - two handshake signals
are used to synchronize the data transfer. One
signal, call it H1, is asserted by the interface
chip. The other signal, call it H2, is asserted
by the I/O device. - two handshake modes are
available -- pulse mode and interlocked mode.
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Input Handshake Protocol Step 1. The interface
chip asserts (or pulses) H1 to indicate its
intention to input data. Step 2. The input device
puts data on the data port pins and also asserts
(or pulses) the handshake signal H2. Step 3.
The interface chip latches the data and
de-asserts H1. After some delay, the input
device also de-asserts H2.
H1
Data
Valid data
H2
(a) Interlocked
H1
Data
valid data
H2
(b) Pulse mode
Figure 7.3 Input handshakes
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Output Handshake Protocol Step 1. The interface
chip places data on the port pins and asserts (or
pulses) H1 to indicate that it has valid data to
be output. Step 2. The output device latches the
data and asserts (or pulses) H2 to acknowledge
the receipt of data. Step 3. The interface chip
de-asserts H1 following the assertion of H2. The
output device then de-asserts H2.
H1
valid data
Data
H2
(a) Interlocked
H1
valid data
Data
H2
(b) Pulse mode
Figure 7.4 Output handshaking
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68HC11 Parallel I/O Overview - The 68HC11A8 has
40 I/O pin that are arranged in five I/O
ports. - All I/O pins serve multiple
functions. - Ports A, B, and E with the exception
of port A pin 7 are fixed-direction inputs or
outputs. - Ports C and D are bi-directional I/O
pins under the control of their associated
data direction registers. - Port C, port B, the
STRA pin, and the STRB pin are used for strobed
and handshake parallel I/O, as well as for
general-purpose I/O. Port Registers - To input,
the 68HC11 reads from the port data register - To
output, the 68HC11 writes into the port data
register - All except port C have one data
register PORTA (at 1000) PORTB (at
1004) PORTC (at 1003) PORTCL (at
1005) PORTD (at 1008) PORTE (at 100A)
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Fixed Direction I/O (ports A, B, and E) To input
from an input port, execute a load instruction
with the port data register as the
source operand. For example, the following
instruction sequence reads a byte from port
E REGBAS equ 1000 I/O register block base
address PORTE equ 0A offset of port E data
register from REGBAS ldx REGBAS ldaa PORTE,X
To output a byte to an output port, write to the
port data register directly. For example, the
following instruction sequence outputs the value
38 to port B REGBAS equ 1000 I/O register
block base address PORTB equ 04 offset of port
B data register from REGBAS ldx REGBAS ldaa
38 staa PORTB,X
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Bidirectional I/O (Ports C and D) - Each pin of
ports C and D has an associated bit in a specific
data register and another in a data direction
register. - The primary direction of a pin is set
by its associated bit in the data direction
register. - When an output pin is read, the value
at the input to the pin driver is returned. - The
data direction registers are cleared by reset to
configure all bidirectional I/O pins
for input. - Before performing I/O operation to
these two ports, the software should set up
the data direction registers of these two
ports. Example 6.1 Write an instruction sequence
to output the value CD to port
D. Solution REGBAS equ 1000 PORTD equ 08 DDRD
equ 09 ldx REGBAS ldaa 3F set up the
directions of port D pins staa DDRD,X
ldaa CD output CD to port
D staa PORTD,X
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Parallel I/O Control Register (PIOC) - All
strobed mode I/O and handshake I/O are controlled
by this register
7 6 5 4 3
2 1 0
at 1002
STAI
STAF
CWOM
HNDS
OIN
PLS
EGA
INVB
value after reset
0 0 0 0
0 U 1 1
undefined
STAF Strobe A flag. This bit is set when a
selected edge occurs on the STRA pin This flag
is cleared by first reading the PIOC register
followed by reading the PORTCL register STAI
Strobe A interrupt enable CWOM port C wired-or
mode select HNDS handshake/strobe mode select (0
for strobe mode, 1 for handshake
mode) OIN output/input handshake select (0 for
input handshake, 1 for output handshake) (releva
nt only when HNDS is 1) PLS pulse/interlocked
handshake select (0 for interlocked handshake, 1
for pulse mode handshake). This bit is relevant
only when the HNDS bit is 1. EGA active edge
select for STRA. (0 for falling, 1 for rising
edge) INVB invert strobe B. (0 selects low as
active level. 1 selects high as active level)
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Strobe Input Port C - Strobe mode I/O is
selected when the bit 4 of the PIOC register is
set to 0 and port C becomes a strobe input
port. - The bit 1 of the PIOC register selects
the active edge of the STRA pin. - The active
edge of the STRA signal latches the values of the
port C pins into the PORTCL register. - Reading
the PORTC register returns the current values on
the port C pins. - Reading the PORTCL register
returns the contents of the latch PORTCL. - When
enabled, the active edge of the STRA signal will
generate an interrupt to the 68HC11.
STRA (in)
tIH
tIS
PORTC (in)
tIH input setup time (60 ns at 2 MHz E
clock) tIS input hold time (100 ns at 2 MHz E
clock)
Figure 7.5 Port C strobe input timing
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Strobed Output Port B The STRB signal is the
strobe signal that is pulsed for two E clock
cycles each time there is a write to port B.
MCU write to PORT B
E
tPWD
Port B
new port data
previous port data
tDEB
STRB
for 2 E cycles
tPWD peripheral data write delay time tDEB F
fall to STRB valid delay time
Figure 7.6 Port B strobe output timing
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Port C Input Handshake Protocol
read PORTCL
E
READY
tDEB
STRB
tAEB
tIH
STRA
tIS
PORTC
tAEB STRA asserted to E fall
tDEB E fall to STRB delay
tIH Port C data hold time
tIS Port C data setup time
Figure 7.7 Port C interlocked input handshaking
- STRA is a latch command asserted by an input
device (active edge is rising in the
figure). - STRB is a ready output driven by the
68HC11 (active high in the figure). - When ready
for accepting new data, the 68HC11 asserts (or
pulses) STRB pin. - The input device places data
on input port pins and asserts the STRA signal.
The active edge of STRA latches the data into
the PORTCL register, sets the STAF flag in
PIOC register and de-asserts the STRB signal.
The de-assertion of STRB inhibits external
device from strobing new data into port C. - Not
until the 68HC11 reads PORTCL, new data cannot be
applied on port C pins.
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Port C Output Handshake Protocol
write PORTCL
E
tPWD
PORT C
tDEB
tDEB
READY
STRB
tAES
STRA
tPWD peripheral data write delay time, 150 ns
max at 2 MHz
tDEB E fall to STRB delay, 225 ns at 2 MHz
tAES STRA asserted to E fall setup time, 0 ns
at 2 MHz
Figure 7.8 Port C interlocked output handshake
timing
- STRA is an acknowledge input (driven by the
external device) - STRB is a ready output (driven
by the 68HC11) - In this figure, the active edge
of STRA is rising and the active level of STRB is
high. - The 68HC11 writes data into PORTCL and
then asserts STRB to indicates there are
valid data on port C pins - The external device
then asserts STRA to acknowledge the receipt of
data which will then cause STRB to be
de-asserted and the STAF flag to be set. - After
the de-assertion of STRB, STRA is also
de-asserted.
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Simple Input Devices Examples of input devices
include switches, analog-to-digital converter,
keyboards, etc..
Example 7.2 Connect an 8-DIP switch to port E of
the 68HC11 and read a byte from it.
VCC
Solution REGBAS equ 1000 PORTE equ
0A LDX REGBAS LDAA PORTE,X . . .
10 KW
68HC11
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
SW DIP-8
Figure 7.9 Connecting a set of eight DIP switches
to port E
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Interfacing Parallel Ports to the Keyboard - A
keyboard is arranged as an array of switches,
which can be mechanical, membrane, capacitive,
or Hall-effect in construction. - In mechanical
switches, two metal contacts are brought together
to complete a circuit. - Mechanical switches have
a problem called contact bounce. A series of
pulses are generated because the switch
contacts do not come to rest immediately. - The
response time of the switch is several orders of
magnitude slower than that of a computer. - A
debouncing process is needed to solve the contact
bounce problem.
VCC
5 to 20 ms
H
L
To computer
active low output
Figure 6.10 Contact bounce
Keyboard input procedure Step 1. Keyboard
scanning to find out which key has been
pressed. Step 2. Key debouncing to make sure a
key was pressed. Step 3. Table lookup to find the
ASCII code of the key that has been pressed.
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Keyboard Scanning Techniques - A keyboard with
more than a few keys is often arranged as a
matrix of switches that uses two decoding and
selecting devices to determine which key was
pressed. - An example of 64-key keyboard is shown
in Figure 6.11.
10KW each
MC14051
X7
inhibit
X6
5 V
X5
68HCC11
X4
PC7
X3
X
C B A
X2
PC5
X1
PC4
X0
PC3
PC2
C
PC1
74LS138
B
A
PC0
Figure 7.11 Keyboard Structure
- The MC14051 is an analog mux and is used to
select the row. - The 74LS138 selects the
column. - PC5-PC3 select the row and PC2-PC0
select the column to be scanned. - X7-X0 are
pulled up to 5 V by the pull-up resistors. - The
decoder 74LS138 outputs are asserted low. - A
pressed key will send a low to the X output to
the port C pin 7 and hence can be detected.
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The program to scan the keyboard in Figure
7.11 Pins PC7 should be configured for input
while PC5-PC0 should be configured for
output. REGBAS equ 1000 base address of I/O
register block DDRC equ 07 offset of port C
data direction register from REGBAS KEYBD equ 03
port C is used as keyboard ldaa 3F set
up port C pin directions staa DDRC,X resetc
clr KEYBD,X start from row 0 and column
0 scan brclr KEYBD,X 80 debnce detect a
pressed key brset KEYBD,X 3F resetc need to
reset the row and column count inc KEYBD,X
check the next row or column bra scan end
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Keyboard Debouncing - The signal output from the
key switch falls and rises a few times within a
period of 5 ms as the contact bounces. - A human
being cannot press and release a key in less than
20 ms, a debouncer will recognize that the
switch is closed/open after the voltage is
low/high for 10 ms. - Both hardware and software
debouncing techniques are available.
VDD
Set
Q
Q
R
Hardware debouncing techniques 1. Set-reset
flip-flops 2. Noninverting CMOS gates with
high-input impedance 3. Integrating debouncers
set
reset
Reset
R
(a) Set-reset flip-flop
VDD
4050
VOUT
VDD
(b) CMOS Gate debouncer
H
VOUT
Threshold voltage
L
switch closed
(c) Integrated RC circuit debouncer
Figure 7.13 Hardware debouncing techniques
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Software Debouncing Techniques The easiest
software debouncing technique is the wait-and-see
technique. After detecting a key switch has
been pressed, this technique simply wait for 10
ms and recheck the same key. REGBAS equ 1000
base address of the I/O register
block KEYBD equ 03 offset of PORTC from
REGBAS TEN_MS equ 2000 loop count for creating
10 ms delay debnce ldy REGBAS ldx TEN_MS wait
10ms nop wait for 10 ms nop dex
bne wait10ms ldaa KEYBD,X recheck the
pressed key bmi scan rescan the keyboard if
the key is not pressed jmp getcode the key
switch is indeed pressed end
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ASCII Code Table Lookup After the key has been
debounced, the keyboard should look up the ASCII
table and send the corresponding ASCII code to
the CPU. keytab fcc 0123456789 fcc ... .
. . fcc getcode ldx REGBAS ldab KEYBD,X
clra andb 3f compute the address of the
ASCII code of the pressed addd keytab key
and leave it in X xgdx ldaa 0,X get
the ASCII code end
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Simple Output Devices A Single Light-Emitting
Diode (LED) - An LED will illuminate when it is
forward biased and has enough current flowing
through it. - The current required to light an
LED brightly ranges from a few mA to more than
ten mA. - The voltage drop across a
forward-biased LED ranges from 1.6V to more
than 2 V. - The voltage drop across the LED with
10 mA current flowing through it is assumed to
be 1.7V in this chapter. - In Figure 6.14, the
74HC04 has an high output 4.9V and a low output
0.1V. A high applied to the input of 74HC04
will light the LED. - The 68HC11 does not have
the current capability to drive the LED. A chip
like the 74HC04 is needed to provide the
required current capability.
5V
330W
74HC04
Figure 7.14 A simple LED connected to a CMOS
inverter through a current- limiting resistor
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The Seven-Segment Display - A seven-segment
display consists of seven LED segments (a, b, c,
d, e, f, and g). - A seven-segment display can
be found in common-cathode or common-anode
type.
(a) seven-segment digit
a b c d e
f g
common cathode
(b) common-cathode seven-segment display
common anode
a b c d e
f g
(c) common-anode seven-segment display
Figure 7.15 Seven-segment displays
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Driving the seven-segment displays with the
68HC11 parallel ports
100W each
68HC11
- A segment requires 10 mA to be lighted
brightly. - A buffer chip like 74ALS244 can be
used to boost the 68HC11s current
capability. - The 74ALS244 has a 3V output when
it is high and a 0.2V output when it is
low. - For the circuit shown in Figure 6.18,
a segment will have a current of 13 mA when it
is lighted. - To display a BCD digit, an
appropriate value must be written to the port
register. The value is listed in Table
6.4. - When multiple digits are to be
displayed, the multiplexing technique is often
used to reduce the number of port pins required.
PB0
a
b
PB1
c
PB2
74ALS244
PB3
d
PB4
e
PB5
f
PB6
g
Figure 7.18 Driving a single seven-segment displ
ay with the 68HC11
Table 7.4 BCD to seven-segment decoder
segments
corresponding hex number
BCD digit
g f e d c b a
0 0 1 1 1 1 1 1 3F 1
0 0 0 0 1 1 0 06 2
1 0 1 1 0 1 1 5B 3 1
0 0 1 1 1 1 4F 4 1 1 0
0 1 1 0 66 5 1 1 0 1
1 0 1 6D 6 1 1 1 1 1 0
1 7D 7 0 0 0 0 1 1 1
07 8 1 1 1 1 1 1 1
7F 9 1 1 0 1 1 1 1
6F
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Using Multiplexing Method to Display Multiple BCD
Digits
5
4
100W
0
a
a
a
100W
b
b
b
. .
. . .
. . .
. . .
100W
g
74ALS244
g
g
PB6
PB0
PB1
common cathode
common cathode
common cathode
1KW
PD5
2N2222
1KW
Imax 91 mA
PD4
1KW
PD0
68HC11
Figure 7.19 Port B and D together drive six
seven-segment displays
- The 2N2222 can sink 100-300 mA of current and
can handle the maximum current (91 mA) flowing
into the collector from the common cathode.
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How the Multiplexing Method Works - Port B
drives the segment pattern while port D selects
the corresponding display to be lighted. - To
light the display 5,,0, the corresponding
value to be written into port D are 20, 10,
08, 04, 02, and 01 respectively. For
example, the following instruction sequence
will display the digit 6 on the display
3 REGBAS equ 1000 base address of I/O
register block PORTB equ 04 offset of PORTB
from REGBAS PORTD equ 08 offset of PORTD
from REGBAS DDRD equ 09 offset of DDRD from
REGBAS six equ 7D segment pattern of
6 third equ 08 value to allow display 3 to
light output equ 3F org C000 ldx REGBAS
ldaa output configure port D for output
staa ddrd,X ldaa six send the
segment pattern of 6 to port B staa PORTB,X
ldaa third select display 3 to be
lighted staa PORTD,X end
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The key idea for displaying multiple digits in
the circuit in Figure 6.19 is lighting in
turn each digit for a short period of time and
then switching to the next digit. Repeat this
operation continuously, all displays will appear
to be lighted simultaneously due to the
persistence of vision.
Example 7.5 Display 123456 on the six
seven-segment displays shown in Figure
6.19. Solution The first step is to build a
table of segment patterns (to port B) and display
selection values (to port D).
This Table can be set up by the following
assembler directives org 00 display FCB 0
6,20 FCB 5B,10 FCB 4F,08 FCB 66,04
FCB 6D,02 FCB 7D,01
Seven-segment Displayed display
BCD digit Port B Port D
5 1 06 20 4 2 5B 10 3 3 4F
08 2 4 66 04 1 5 6D
02 0 6 7D 01
The program in the next transparency will step
through each entry of the table, write the
first byte to port B and the second byte to port
D and wait for a short period of time (say 1 ms)
and then move to the next entry.
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regbas equ 1000 PORTB equ 04 PORTD equ
08 DDRD equ 09 output equ 3F org
00 display fcb 06,20 fcb 5B,10 fcb
4F,08 fcb 66,04 fcb 6D,02 fcb
7D,01 org C000 ldx regbas ldaa
output staa ddrd,X forever ldy
display next ldaa 0,Y ldx regbas staa
PORTB,X
ldaa 1,Y staa PORTD,X iny iny ldx
200 loop to delay for 1 ms again nop no
p dex bne again cpy
display12 end of table? beq forever bra
next light the next display end
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Microprocessor or microcontroller Should a
designer use an 8-bit microprocessor along with
one or several peripheral chips or use an 8-bit
microcontroller to implement an embedded
product? These two approaches are compared in
four criteria 1. Product size microcontroller
is certainly smaller. 2. Power consumption a
microcontroller such as the 68HC11A8 consumes
only about 150 mW while an 8-bit microprocessor
such as the Motorola 6802 consumes more than a
watt. 3. Product reliability a design with more
external wires will be less reliable. 4. Design
time much less timing and loading consideration
are involved in the microcontroller approach
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The 68HC24 Port Replacement Unit - In the early
years of the 68HC11, the amount of on-chip EPROM
or EEPROM that can be implemented onto the
microcontroller chip is very limited. - The
software of the target embedded product was to be
placed in the on-chip ROM. - During the product
development stage, software need to be modified
many times. The expanded mode must be chosen
and external EPROM must be used so that software
can be modified and tested. - Ports B and C,
which were needed in the final product, were lost
in the expanded mode during the product
development phase. - The port replacement unit
68HC24 was designed to regain ports B and C so
that the products can be evaluated and
tested. - After the design had been tested and
evaluated to be satisfactory, the software in the
external EPROM could be moved into the internal
ROM without modification as long as the
external EPROM and internal ROM occupied the same
memory space. - The signals and an example of the
68HC24 application is shown in Figure 6.38.
33
VDD
68HC11
68HC24
IRQ
IRQ
AS
AS
PB0-PB7
AD0-AD7
PC0-PC7
STRA
STRB
CS
PB3
PC0-PC7
A12-A15
PB4-PB7
E
E
R/W
R/W
RESET
RESET
from reset circuit
Figure 7.38 Circuit connecting the 68HC11 and the
68HC24