Test 3 May 4

1
Test 3 May 4

• Ch 5,6,7,8
• ASM Chart realization
• Microprogramming an SM chart
• Highlight paths in FPGA
• Shannons expansion
• FP format conversions, add, mult procedure
• Signal Resolution, IEEE 9 valued logic,
  Mapping/Placement/Routing Definitions

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Chapter 10 - Testing
Test circuits for faults Bed of Nails tester for
boards ICs do not provide access to internal
state Only inputs and outputs at pins Bring
internal test points out Controllability and
Observability Automatic Test Pattern Generators
(ATPG) Boundary Scan (B-scan) Built In Self
Test (BIST)
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CH 10

• Covers
• 339-352
• 361-365
• HW due May 5, 4 pm
• 10.1, 10.3, 10.10

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Testing Combinational Logic Stuck at faults
s-a-1 and s-a-0 faults for AND and OR gates
5
Testing an AND-OR Network
How many tests (input combinations) are required
to test this circuit exhaustively?
6
Find Test Vectors for circuit in Figure 10-2

• Procedure to find minimum set of test vectors
• Select an untested fault
• Determine required inputs for that fault
• Determine additional faults that are tested
• Repeat until tests for all faults are found
• Eg
• a b c d e f g h i Faults Tested
• 1 1 1 0 X X 0 X X a0, b0, c0, p0

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Test Vectors for Figure 10-2

• a b c d e f g h i Faults Tested
• 1 1 1 0 X X 0 X X a0, b0, c0, p0
• 0 X X 1 1 1 0 X X d0, e0, f0, q0
• 0 X X 0 X X 1 1 1 g0, h0, i0, r0
• 0 1 1 0 1 1 0 1 1 a1, d1, g1, p1, q1, r1
• 1 0 1 1 0 1 1 0 1 b1, e1, h1, p1, q1, r1
• 1 1 0 1 1 0 1 1 0 c1, f1, i1, p1, q1, r1

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Testing Multi-level circuits -Fault Detection by
Path Sensitization
Path a-m-n-p has been sensitized
Choose a set of inputs that excite the
fault Propagate the effect of the fault to the
output Back propagate to get correct inputs for
all inputs
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Multi-level network Network for Stuck-at Fault
Testing
Test for p s-a-1 Set p0 if p1 due to
fault, it should propagate to o/p So c0 w1
For p0, a or b0 Chose a0 For w1, either u
or t1 For u1, r and d 1 So test vector
A,B,C,D 0101 -gt Also Tests a1,c1,v1,f1
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Tests for Stuck-at Faults in Figure 10-4

• Normal Gate Inputs
• A B C D a b p c q r d s t u v w Faults Tested
• 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 1 a1 p1 c1 v1
  f1
• 1 1 0 1 1 1 1 0 0 1 1 1 0 1 1 1 a0 b0 p0 q1 r0
  d0 u0 v0 w0 f0
• 1 0 1 1 1 0 0 1 1 0 1 0 1 0 1 1 b1 c0 s1 t0 v0
  w0 f0
• 1 1 0 0 1 1 1 0 0 1 0 1 0 0 1 0 a0 b0 d1 s0 t1
  u1 w1 f1
• 1 1 1 1 1 1 1 1 1 0 1 1 0 0 1 0 a0 b0 q0 r1 s0
  t1 u1 w1 f1

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Testing Sequential Circuits

• All state transitions and outputs need to be
  verified
• Some times, only outputs can be observed, but not
  states of flip flops
• Assume reset available to get to start state

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Convert Sequential Circuits Devise tests for
combinational
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Lets say we need to test the Sequential Circuit
in fig
Does X 0 1 0 1 1 0 0 1 1 Test all
transitions? Assume reset possible Z 0 0 1 0
1 1 1 1 0 What if S3-gt S0 replaced With S3 -gt
S3 Need better ways to test
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Testing Strongly Connected State Graphs

• Strongly connected graphs a state graph in
  which every state can be reached from every other
  state
• Find a distinguishing input sequence
• Gives different outputs depending on state
• Verify every entry in the state table by
• going to reset state,
• giving inputs to reach particular state,
• then distinguishing sequence to check it

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Sequential CircuitExample

• Q1Q2 P.S N.S Output
• X 0 1 X 0 1
• 00 S0 S0 S1 0 0
• 10 S1 S0 S2 1 1
• 01 S2 S3 S3 1 1
• 11 S3 S2 S0 1 0
•  

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Sequential CircuitExample

• Q1Q2 P.S N.S Output
• X 0 1 X 0 1
• 00 S0 S0 S1 0 0
• 10 S1 S0 S2 1 1
• 01 S2 S3 S3 1 1
• 11 S3 S2 S0 1 0
•  

Distinguishing Sequence 11 S001 S111 S210 S3
00
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Sequential CircuitExample

• Q1Q2 P.S N.S Output
• X 0 1 X 0 1
• 00 S0 S0 S1 0 0
• 10 S1 S0 S2 1 1
• 01 S2 S3 S3 1 1
• 11 S3 S2 S0 1 0
•  

Distinguishing Sequence 11 S001 S111 S210 S3
00
Example Test R 1 1 1 1 0 1 1 0
(S1 to S2)
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Test Vectors for Sequential Ckt

• Input Output Transition Verified
• R 0 1 1 0 0 1 (S0 to S0)
• R 1 1 1 0 1 1 (S0 to S1)
• R 1 0 1 1 0 1 0 1 (S1 to S0)
• R 1 1 1 1 0 1 1 0 (S1 to S2)
• R 1 1 0 1 1 0 1 1 0 0 (S2 to S3)
• R 1 1 1 1 1 0 1 1 0 0 (S2 to S3)
• R 1 1 0 0 1 1 0 1 1 1 1 0 (S3 to S2)
• R 1 1 0 1 1 1 0 1 1 0 0 1 (S3 to S0)

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Scan Testing

• Sequential Circuit testing simplified if state of
  flip-flops can be observed
• Lots of pins needed
• Solution Arrange all flip-flops to form a shift
  register
• Single serial output pin sufficient
• Scan Path testing

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Scan Path Test Circuit Using Two-port Flip-flops
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Test Procedure

•  1. Scan in the test vector Qi values via SDI
  using the test clock TCK.
• 2. Apply the corresponding test values to the Xi
  inputs.
• 3. After sufficient time for the signals to
  propagate through the combinational network,
  verify the output Zi values.
• 4. Apply one clock pulse to the system clock SCK
  to store the new values of Qi into the
  corresponding flip-flops.
• 5. Scan out and verify the Qi values by pulsing
  the test clock TCK.
• 6. Repeat steps 1 through 5 for each test vector.
•  
• Steps 5 and 1 can overlap, since it is possible
  to scan in one test vector while scanning out the
  previous test result.

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One row of the state transition table

• One row of the state transition table is as
  follows
•  
• Q1Q2Q3 Q1Q2Q3 Z1Z2
• X1X2 00 01 11 10 00
  01 11 10
• 101 010 110 011 111 10 11 00 01
•  

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Timing Chart for Scan Test
Q1Q2Q3 Q1Q2Q3 Z1Z2
X1X2 00 01 11 10 00 01 11 10
101 010 110 011 111 10 11 00
01
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System with Flip-flop Registers and Combinational
Logic Blocks
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Scan Test Configuration with Multiple ICs
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IC with Boundary Scan Register and Test-access
Port
Standard for Boundary Scan Testing IEEE Standard
1149.1 JTAG (Joint Test Action Group)
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JTAG Test-access Port (TAP)
Standard for Boundary Scan Testing IEEE Standard
1149.1 developed by JTAG (Joint Test
Action Group) 5 pins devoted to Test Access Port
(TAP) TDI Test Data Input TCK Test Clock TMS
Test Mode Select TDO Test Data Out TRST
Test Reset
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PC Board with Boundary Scan ICs
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Typical Boundary Scan Cell
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Generic BIST Scheme
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Self-test Circuit for RAM
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Self-test Circuit for RAM with Signature Register
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4-bit Linear Feedback Shift Register (LFSR)
How many patterns can n-bit shift register
generate? Ring counter ? Johnsonss ring
counter?
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Ring Counters
How many patterns can n-bit shift register
generate? Ring counter Circular shift register
n patterns 0001 1000 0100 0010 back to
0001 Johnsonss ring counter Q as opposed to
Q 0001 0000 1000 1100 1110 1111 0111
- 0011 back to 0001
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Patterns Generated by the LFSR

• Proper choice of feedback outputs through the
  exclusive OR gate
• Generate 2n 1 different bit patterns using an
  n-bit shift register.
• All possible patterns can be generated except for
  all 0s. The patterns generated by the LFSR of
  Figure 10-23 are
• 1000, 1100, 1110, 1111, 0111, 1011, 0101, 1010,
  1101, 0110, 0011, 1001, 0100, 0010, 0001, 1000, .
  . .
• Pseudo Random Number Generator

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Feedback for Maximum-length LFSR Sequence

• n Feedback
• 4,6,7 Q1 Å Qn
• 5 Q2 Å Q5
• 8 Q2 Å Q3 Å Q4 Å Q8
• 12 Q1 Å Q4 Å Q6 Å Q12
• 14,16 Q3 Å Q4 Å Q5 Å Qn
• 24 Q1 Å Q2 ÅQ7 Å Q24
• 32 Q1 Å Q2 Å Q22 Å Q32

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Modified LFSR with 0000 State
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Multiple-input Signature Register (MISR)
Test data XORed into the register with each
clock Eg 1010, 0001, 1110, 1111, 0100, 1011,
1001, 1000, 0101, 0110, 0011, 1101, 0111, 0010,
1100 Leads to signature 1010 Any sequence
differing in 1-bit will lead to different
signature
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BIST Using BILBO Registers
One Ckt behaves as PRPG (Pattern
Generator) Other one as MISR