EECE 631 Microcomputer System Design Lecture 21: Timing

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EECE 631Microcomputer System DesignLecture 21
Timing

• Spring 2008
• Chris Lewis
• clewis_at_ksu.edu

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Next Parameter Twr
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Twr mins0
Address must Be valid at end Of WE pulse
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Add to CPU timing diagram
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Inequality

• SMC_17_min gt Twr
• 8gt0 OK

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Next Parameter Twhz
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Twhz mins0, max20,25

• How long can memory
• Stay on the data buss
• After a read, going into A write?
• 3 different terms
• Each guarantee
• Memorys withdraw
• After WE (Twhz)
• After CS (Thz)
• After OE (Tohz)

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Fundamental Understanding

• If any one of these conditions satisfies the
  CPUs requirements then Memory will be off in
  time
• Even though we have 3 different inequality
  constraints, not all have to be satisfied.

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Twhz on CPU timing diagram?
SMC 19-23 provide Min times relative to rise of
write pulse In which cpu provided data will be
valid
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Twhz and Tohz provide maximum time after some
signal In which memory will relinquish the buss
NRD
SMC22 Min.5Tcpmck -5.2
CPU provided data
SMC20 minnTcpmck -.5
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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Which parameter Guarantees that memory will be
off the buss first, Twhz or Tohz?
NRD
CPU provided data
Smc20 minnTcpmck -.5
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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Parameters are given relative to input signals

• Tohz max(20,30) is given relative to the rising
  edge of the previous read pulse
• Twhz max(20,25) is given relative to the falling
  edge of the current write pulse
• When, relative to the clock do these two pulses
  occur?

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When does Memory give up Control?
SMC 38 provide Min times before CS becomes
active that the read pulse rising edge occurs
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ADD SMC38 to picture to give time reference for
Tohz
SMC38
NRD
CPU provided data
Smc20 minnTcpmck -.5
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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When does NWR rise?
SMC 18 provide Min times before CS becomes
active that the read pulse rising edge occurs
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ADD SMC18 to picture
SMC18
SMC38
NRD
CPU provided data
SMC20
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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When does NWR fall?
SMC 18 SMC27 provide Min time Falling edge of
NWR occurs relative To rising edge of chip select
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ADD SMC27 to picture SMC18 and SMC27 give time
reference to NWR leading edge
SMC18
SMC27
SMC38
NRD
CPU provided data
SMC20
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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ADD SMC7 to picture This relates both edges to a
single event, NCS falling
SMC7
SMC18
SMC27
SMC38
NRD
CPU provided data
SMC20
memory provided data
Twhz min0,max(20,25)
Tohz min 0,max(20,30)
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The inequalities

• Relative to the start of the write cycle,
  (falling edge of Chip Select), the cpu takes
  control of the data buss at this time
• SMC7 - SMC18 - SMC20
• Relative to the start of write cycle, (falling
  edge of Chip Select), the memory guarantees HighZ
  at these times
• SMC38Tohz
• SMC7 -SMC18-SMC27Twhz
• Two inequalities
• SMC38Tohz lt SMC7 - SMC18 - SMC20
• SMC7 - SMC18 - SMC27 Twhz lt SMC7 - SMC18 -
  SMC20
• -SMC27 Twhz lt - SMC20

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Guaranteed to have contention

• Relative to the start of the write cycle,
  (falling edge of Chip Select), the cpu takes
  control of the data buss at this time
• SMC7 - SMC18 - SMC20 (n1)Tcpmck-5.5-nTcpmck-.5
  Tcpmck-5ns
• This is the latest time the cpu will take over
  not earliest time
• Data is guaranteed to be valid at this time
• Relative to the start of write cycle, (falling
  edge of Chip Select), the memory guarantees HighZ
  at these times
• SMC38Tohz This is a good guarantee (23,33)ns
• SMC7 -SMC18-SMC27Twhz
• This is a good guarantee if SMC7 is taken without
  rise and falls
• (n1)Tcpmck-5.5-(n)Tcpmck-2.5(20 or25)
• Tcpmck 22ns for 70ns memory
• Tcpmck 17ns for 55ns memroy
• Two inequalities
• (23,33) lt Tcpmck-5ns
• Tcpmck 22ns lt. Tcpmck-5ns

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Need to add data float wait states

• How many need to be added?
• Consider the effect on the following
• Array0 10 // first write
• Array1 20 // second write
• V 0x8E // read followed by write