Instructor: Nachiket M. Kharalkar

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Introduction to Microcontrollers

• Instructor Nachiket M. Kharalkar
•  
• Lecture 4
• Date 06/08/2007
• E-mail knachike_at_ece.utexas.edu
•  

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Todays Agenda

• Get boards from Daryl Goodnight (ENS 234)
• Recap
• Addressing modes
• Simplified execution

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Recap

• Program file (.rtf) source code.
• TheLog.rtf logs information
• TheList.rtf the assembly listing
• TheCRT.rtf the input/output data of a CRT
  terminal
• Microcomputer file (.uc) internal microcomputer
• I/O Device file (.io) external I/O devices
  switches, LEDs, LCDs, keyboard, the CRT, motors,
  IR and sensors.
• Stack file (.stk) holds temporary information
• Scope file (.scp) used for debugging
• Plot file (.plt) display graphical information

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Texas Simulator Debugging

• Single step through the program by pressing F10
• Create break point by entering address in the
  microcomputer window and press add OR by right
  clicking in the list file window

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The simplified execution has five phases
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Simulated 6812 machine language execution
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During a read cycle (R/W1)

• memory at specified address puts information on
  data bus, and
• processor transfers information into appropriate
  place within the processor.
• instruction fetch. The address is the PC and the
  8-bit data is loaded into the instruction
  register, IR.
• operand fetch. The address is also the PC, but
  the 8-bit data is used to calculate the effective
  address.
• data fetch. The address is the EAR, and the 8-bit
  data is loaded into a register or sent to the
  ALU.
• stack pull. First, the 8-bit data is read from
  memory pointed to by SP and stored in a register,
  then the stack pointer is incremented SPSP1.

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During a write cycle (R/W0)

• processor puts information on data bus, and
• memory transfers information into specified
  location
• data write. The 8-bit data from a register or ALU
  is stored in memory at the address specified by
  the EAR.
• stack write. First, the stack pointer is
  decremented SPSP-1, then the 8-bit data from a
  register is stored in memory at the address
  specified by the SP.

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Addressing modes

• Where to find the data?
• inherent no operand or implied operand
• immediate in the instruction itself
• direct or extended absolute address of the data
• Indexed addressing mode
• relative where to go for branch instructions

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Inherent addressing mode

• Inherent addressing mode has no operand field
• sometimes there is no data
• ex- stop
• sometimes the data for the instruction is
  implied.
• ex- clra
• sometimes the data must be fetched, but the
  address is implied
• ex- pula

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Immediate addressing mode

• Immediate addressing mode uses a fixed data
  constant

Opcode fetch R 0xF801 0x86 from EEPROM Operand
fetch R 0xF802 0x24 from EEPROM
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Direct Page addressing mode

• Direct Page addressing mode
• uses an 8-bit address
• access from addresses 0 to 00FF
• called zero-page.
• on the 6812 they reference the I/O ports
• the

Opcode fetch R 0xF801 0x96 from EEPROM Operand
fetch R 0xF802 0x36 from EEPROM Fetch using EARR
0x0036 0x57 from I/O
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Extended addressing mode

• uses a 16-bit address
• size of data depends on the op code (which
  register is uses)
• access all memory and I/O devices
• outside Motorola family this addressing mode is
  called direct
• the operator forces extended addressing

Opcode fetch R 0xF801 0xB6 from EEPROM Operand
fetch R 0xF802 0x08 from EEPROM Operand fetch R
0xF803 0x01 from EEPROM Fetch using EARR 0x0801
0x62 from RAM
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PC Relative addressing mode

• used for the branch instructions
• stored in the machine code is not the absolute
  address
• but the 8-bit signed offset relative distance
  from the current PC value
• the PC already points to the next instruction
• the assembler calculates it for us

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Backward branch

• 1) address of current instruction
• F880 bra F840
• 2) op code of branch instruction, and size of
  instruction
• F880 20rr bra F840
• 3) address of next instruction
• F880 20rr bra F840
• F882
• 4) calculate PC relative addressing
• rr destination address of next instruction
• F840 - F882 -42 BE
• The object code for this instruction will be
  20BE.

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Forward branch

• 1) address of current instruction
• F000 bra F044
• 2) op code of branch instruction, and size of
  instruction
• F000 20rr bra F044
• 3) address of next instruction
• F000 20rr bra F044
• F002
• 4) calculate PC relative addressing
• rr destination address of next instruction
• F044 - F002 42
• The object code for this instruction will be
  2042

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Branch out of range

• 1) address of current instruction
• F000 bra F144
• 2) op code of branch instruction, and size of
  instruction
• F000 20rr bra F144
• 3) address of next instruction
• F000 20rr bra F144
• F002
• 4) calculate PC relative addressing
• rr destination address of next instruction
• F144 - F002 142
• Branch out of range assembly error.

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Indexed addressing mode

• Fixed offset with the 16-bit registers X, Y, SP,
  or PC
• 5-bit constant offset (-16 to 15)
• 9-bit constant offset (-256 to -16 OR 16 to 255)
• 16-bit unsigned (0 to 65535) or signed
• (-32768 to 32767.)
• Auto Pre/Post increment/decrement (-8 to -1 OR 1
  to 8)

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5-bit constant offset (-16 to 15)
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9-bit constant offset (-256 to -16 OR 16 to 255)
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16-bit unsigned (0 to 65535) or signed (-32768
to 32767)
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Auto Pre/Post increment or decrement (-8 to -1 OR
1 to 8)

• uses the 16-bit registers X, Y, or SP.
• register is modified either before (pre) or
  after (post)
• amount added to (subtracted from) 1 to 8
• In each case assume Reg Y is initially 2345.
• Post-increment examples
• staa 1,Y 2345RegA, then Reg Y2346
• staa 4,Y 2345RegA, then Reg Y2349
• Pre-increment examples
• staa 1,Y Reg Y2346, then 2346RegA
• staa 4,Y Reg Y2349, then 2349RegA
• Post-decrement examples
• staa 1,Y- 2345RegA, then Reg Y2344
• staa 4,Y- 2345RegA, then Reg Y2341
• Pre-decrement examples
• staa 1,-Y Reg Y2344, then 2344RegA
• staa 4,-Y Reg Y2341, then 2341RegA

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