Figure 2'1' A binary switch'

1
x
1

x
0

(a) Two states of a switch
S
x
(b) Symbol for a switch
Figure 2.1. A binary switch.
2
S
Battery
Light
x

(a) Simple connection to a battery
S
Power
Light
x

supply
(b) Using a ground connection as the return path
Figure 2.2. A light controlled by a switch.
3
S
S
Power
x1
x2
Light


supply


(a) The logical AND function (series connection)
S
x1


Power
Light
supply
S
x2


(b) The logical OR function (parallel connection)
Figure 2.3. Two basic functions.
4
Figure 2.4. A series-parallel connection.
5
Figure 2.5. An inverting circuit.
6
Figure 2.6. A truth table for the AND and OR
operations.
7
Figure 2.7. Three-input AND and OR operations.
8
x
1
x
2
x
1
x
x
¼
x



x
x

1
2
n
1
2
x
2
x
n
(a) AND gates
x
1
x
2
x
1
x
x
¼
x



x
x

1
2
n
1
2
x
2
x
n
(b) OR gates
x
x
(c) NOT gate
Figure 2.8. The basic gates.
9
x
1
x
2
f
x
x

(
)
x


1
2
3
x
3
Figure 2.9. The function from Figure 2.4.
10
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.10. An example of logic networks.
11
Figure 2.11. Proof of DeMorgans theorem in 15a.
12
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.12. The Venn diagram representation.
13
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.13. Verification of the distributive
property.
14
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.14. Verification of
x
y
x

z
y
z

x
y
x

z.





15
Figure 2.15. A function to be synthesized.
16
x
1
x
2
f
(a) Canonical sum-of-products
x
1
f
x
2
(b) Minimal-cost realization
Figure 2.16. Two implementations of a function
in Figure 2.15.
17
Figure 2.17 Three-variable minterms and
maxterms.
18
Figure 2.18. A three-variable function.
19
x
2
f
x
3
x
1
(a) A minimal sum-of-products realization
x
1
x
3
f
x
2
(b) A minimal product-of-sums realization
Figure 2.19. Two realizations of a function in
Figure 2.18.
20
Figure 2.20. NAND and NOR gates.
21
Figure 2.21. DeMorgans theorem in terms of
logic gates.
22
Figure 2.22. Using NAND gates to implement a
sum-of-products.
23
Figure 2.23. Using NOR gates to implement a
product-of sums.
24
x1
x2
f
x3
(a) POS implementation
x1
x2
f
x3
(b) NOR implementation
Figure 2.24 NOR-gate realization of the
function in Example 2.4.
25
x1
f
x2
x3
(a) SOP implementation
x1
f
x2
x3
(b) NAND implementation
Figure 2.25. NAND-gate realization of the
function in Example 2.3.
26
Figure 2.26. Truth table for a three-way light
control.
27
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.27. Implementation of the function in
Figure 2.26.
28
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.28. Implementation of a multiplexer.
29
Please see portrait orientation PowerPoint file
for Chapter 2
Figure 2.29. A typical CAD system.
30
x
1
x
2
f
x
3
Figure 2.30. A simple logic function.
31
ENTITY example1 IS PORT ( x1, x2, x3 IN
BIT f OUT BIT ) END example1

Figure 2.31. VHDL entity declaration for the
circuit in Figure 2.30.
32
ARCHITECTURE LogicFunc OF example1 IS BEGIN
f lt (x1 AND x2) OR (NOT x2 AND x3) END
LogicFunc
Figure 2.32. VHDL architecture for the entity
in Figure 2.31.
33
Figure 2.33. Complete VHDL code for the circuit
in Figure 2.30.
34
Figure 2.34. VHDL code for a four-input
function.
35
x
1
x
3
f
x
2
g
x
4
Figure 2.35. Logic circuit for the code in
Figure 2.34.
36
x1
x1
x2
x2
x3
x3

(b) Function
B
(a) Function
A
x1
x2
x1
x2
x3


x3


(c) Function
C
(d) Function
f
Figure 2.36. The Venn diagrams for Example 2.11.
37
x
3
x
3
x
x
x
x
1
2
1
2
x
x
4
4
(a)
(b)
Figure P2.1. Two attempts to draw a
four-variable Venn diagram.
38
Figure P2.2. A four-variable Venn diagram.
39
1
x
1
0
1
x
2
0
1
x
3
0
1
f
0
Time
Figure P2.3. A timing diagram representing a
logic function.
40
1
x
1
0
1
x
2
0
1
x
3
0
1
f
0
Time
Figure P2.4. A timing diagram representing a
logic function.